FinFET Drivability Control via Segmented Gate Width

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Solution Overview

Problem

The existing semiconductor integrated circuits with fin transistors have limited flexibility in controlling drivability, as they are designed with fixed gate widths and lengths, restricting the degree of drivability to discrete values, which can lead to reduced performance and design flexibility.

Innovation Solution

The semiconductor integrated circuit design includes transistors with varying numbers of fin transistors connected in series, allowing for different gate lengths and widths, enabling adjustable drivability by changing the number of fin transistors in each transistor, thereby increasing design flexibility and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If transistors have fixed gate width and length, then manufacturing precision is improved, but adaptability deteriorates

Engineering Contradiction:
Improveuniformity in transistor characteristicsVSAvoiddesign flexibility for drivability control
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The transistor gate is segmented into multiple fins, where the number of fins can be varied to achieve different drivability levels. This allows the basic fin structure to remain uniform (maintaining manufacturing precision) while the total gate width is adjusted by changing the number of segmented fin units (improving adaptability).

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the circuit can use transistors with different numbers of fins, allowing local optimization of drivability for different circuit requirements while maintaining uniform manufacturing processes for each transistor type.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If the number of transistors in series or parallel is increased, then drivability control is improved, but device complexity increases

Engineering Contradiction:
Improvedrivability control rangeVSAvoidnumber of transistors
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Instead of changing the number of transistors to adjust drivability, the invention changes the parameter of gate width by varying the number of fins within a single transistor. This achieves continuous drivability adjustment without increasing device complexity from additional transistor instances.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If transistors with different gate lengths and widths are used, then drivability flexibility is improved, but manufacturing precision deteriorates

Engineering Contradiction:
Improvedrivability value rangeVSAvoiduniformity in transistor characteristics
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The gate is divided into identical fin segments that can be replicated in number. Each fin has uniform dimensions ensured by standard manufacturing processes, while the total gate width is controlled by the number of fins, achieving both manufacturing precision and drivability flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate width parameter is adjusted by changing the number of fins rather than the dimensions of individual fins. This maintains uniform fin characteristics for manufacturing precision while achieving variable overall gate width for drivability control.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10600784B2Semiconductor integrated circuit and logic circuit
Publication Date: 2020.03.24 SOCIONEXT INC
  • US10600784B2 patent drawing
  • US10600784B2 patent drawing
  • US10600784B2 patent drawing

AI summary

A semiconductor integrated circuit including a standard cell having a NAND function, the standard cell including: first and second n-channel transistors, and first and second p-channel transistors, wherein the first n-channel transistor includes n fin transistor(s) where n is an integer equal to or greater than one, the first n-channel transistor having its gate connected to a first input node, the n fin transistor(s) forming the first n-channel transistor includes a first fin extending in a first direction and a first gate extending in a second direction perpendicular to the first direction, and the second n-channel transistor includes m fin transistors where m is an integer greater than n, the second n-channel transistor having its gate connected to a second input node, the m fin transistors forming the second n-channel transistor includes a second fin extending in the first direction and a second gate extending in the second direction.