FinFET Dual Vertical Spacer for Fringe Capacitance Reduction
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Solution Overview
Problem
FinFET devices face challenges in reducing parasitic capacitance, particularly fringe capacitance, which does not decrease with scaling, affecting device performance and reliability.
Innovation Solution
A dual vertical spacer structure is implemented, with an ultra-low-k spacer (dielectric constant <4) below the gate and a low-k spacer (dielectric constant 4<k<7) above the gate, providing sufficient etch resistance and reducing fringe capacitance while maintaining reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a single low-k spacer material is used to reduce fringe capacitance, then parasitic capacitance decreases, but etch resistance during contact etch processing becomes insufficient
Solution Approach 1:
The spacer structure is divided into two distinct segments: a first spacer region with low-k material (dielectric constant <4) positioned below the gate to minimize fringe capacitance, and a second spacer region with higher-k material (dielectric constant 4<k<7) positioned above the gate to provide sufficient etch resistance during contact etch processing. This segmentation allows each region to be optimized for its specific function.
Solution Approach 2:
Different dielectric materials are applied to different spatial locations of the spacer structure. The ultra-low-k material is placed in the region where fringe capacitance has the greatest impact (below the gate), while the higher-k material with better etch resistance is placed in the region exposed to etch processing (above the gate). This local differentiation optimizes both capacitance reduction and processing reliability.
2Productivity
If device scaling is performed to improve performance, then gate capacitance decreases, but parasitic fringe capacitance remains constant
Solution Approach 1:
The dielectric constant parameter of the spacer material is changed and optimized. By using ultra-low-k material with dielectric constant less than 4 in the first spacer region, the parasitic fringe capacitance is reduced proportionally with device scaling, allowing continued performance improvement. This parameter change addresses the limitation that traditional materials do not scale favorably with device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual spacer structure effectively reduces fringe capacitance, improving FinFET performance and reliability by optimizing dielectric constants and etch resistance, leading to lower FEOL capacitance and enhanced circuit performance.
Implementation Method 1
a first spacer (530) on the insulator (510) between the gate (504) and the source (502)/drain (506)... the first spacer (530) reducing gate-to-source, gate-to-fin sidewall, and/or gate-to-drain fringe capacitance coupling
Implementation Method 2
the spacer material for the second spacer may have a sufficient etch resistance to a contact etch processing, and wherein the spacer material for the second spacer has a higher etch resistance to the contact etch processing than that of the first spacer
Data Source
AI summary
A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.