FinFET Dual Work Function Metal Gate Structure
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Solution Overview
Problem
Gate-Induced Drain Leakage (GIDL) in MOSFET devices worsens with scaled inversion layer thickness due to miniaturization, making it difficult to suppress leakage through traditional doping methods.
Innovation Solution
A method involving the formation of a semiconductor device with a gate dielectric layer, inner and outer dummy gates, spacers, and sequential deposition of work function metals to modify the inversion layer thickness near the source/drain regions, reducing GIDL by sandwiching the second work function metal between the first work function metals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional doping methods are used to suppress leakage, then device structure remains simple, but GIDL worsens with scaled inversion layer thickness
Solution Approach 1:
The patent applies different work function metals to different regions of the gate dielectric. A first work function metal is deposited on a first portion of the gate dielectric, and a second work function metal is deposited on a second portion, creating locally optimized electrical characteristics that suppress GIDL without requiring complex doping modifications throughout the entire device structure.
Solution Approach 2:
The gate structure is segmented into multiple regions with different work function metals. The gate dielectric is divided into a first portion and a second portion, each receiving a different work function metal deposition. This segmentation allows independent optimization of different gate regions to address the GIDL problem while maintaining overall structural simplicity.
2Length of moving object
If inversion layer thickness is reduced to improve device scaling, then device miniaturization is achieved, but GIDL increases
Solution Approach 1:
The patent changes the work function parameter of the gate metal to compensate for the reduced inversion layer thickness. By selecting work function metals with appropriate energy levels and depositing them on specific portions of the gate dielectric, the effective gate control is enhanced, which suppresses GIDL even when the inversion layer thickness is reduced for device scaling.
3Reliability
If work function metals are deposited on different portions of gate dielectric, then GIDL is reduced, but manufacturing process complexity increases
Solution Approach 1:
The patent uses dummy gates as preliminary structures that are formed before the final work function metal deposition. The inner dummy gate and outer dummy gate provide a template structure that guides the subsequent deposition and patterning of the first and second work function metals. This preliminary action simplifies the manufacturing process by providing a clear structural framework for the complex multi-metal deposition sequence.
Solution Approach 2:
The dummy gates serve as intermediary structures that facilitate the deposition of different work function metals on different portions of the gate dielectric. The inner dummy gate and outer dummy gate act as masking and alignment references during the deposition process, making the complex multi-step metal deposition manageable through intermediate reference structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces GIDL in MOSFET devices by modifying the inversion layer thickness, improving electrical properties and reducing gate leakage currents.
Implementation Method 1
By applying voltage to the gate, the conductivity of the channel region may increase and allow current to flow from the source region to the drain region
Implementation Method 2
depositing a second work function metal
Data Source
AI summary
An embodiment of the invention may include a method for of forming a semiconductor device and the resulting device. The method may include forming a gate dielectric on a gate region of a substrate. The method may include forming an inner dummy gate on a first portion of the gate dielectric. The method may include forming an outer dummy gate adjacent to the inner dummy gate on a second portion of the gate dielectric. The method may include forming spacers adjacent to the outer dummy gate. The method may include removing the outer dummy gate and depositing a first work function metal. The method may include removing the inner dummy gate and depositing a second work function metal.