FinFET Dummy Fin Removal via Selective Etching

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Solution Overview

Problem

The existing process for fin field effect transistors (FinFETs) requires improvement in the removal of unnecessary dummy fins between active areas, particularly at the post-solid-state doping stage, to enhance the fin structure design and fabrication process.

Innovation Solution

A method involving the formation of a semiconductor device with specific layers and regions, including a substrate with distinct regions, formation of fins and dummy fins, solid-state dopant source layers, insulating buffer layers, and an etch process to cut the dummy fin, ensuring the top surface of the dummy fin is lower than the other layers, allowing for efficient removal and planarization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If dummy fins are retained in the dummy region during fabrication, then the solid-state doping process can be uniformly applied across all regions, but unnecessary dummy fins remain between active areas that require post-stage removal

Engineering Contradiction:
Improveuniformity of doping processVSAvoidpresence of unnecessary dummy fins
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The substrate is divided into distinct regions: first region with fins and first dopant source, second region with fins and second dopant source, and dummy region with dummy fin and second dopant source. This segmentation allows the doping process to be applied uniformly across all regions while enabling selective removal of the dummy fin later, as each region is independently structured.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dummy fin in the dummy region is selectively removed after the doping process is complete. The method enables the dummy fin to serve its temporary purpose during fabrication (receiving uniform doping treatment) and then be extracted/removed post-stage, eliminating the complexity of having unnecessary structures in the final device.

Inventive Principle:
Principle #2Taking out (Extraction)

2Device complexity

If the top surface of the dummy fin is kept level with other layers, then the structure remains simple, but the dummy fin cannot be efficiently removed and planarized

Engineering Contradiction:
Improvesimplicity of structureVSAvoidefficiency of dummy fin removal
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The method performs preliminary actions by forming the dummy fin and applying doping treatments to it along with the active fins. The dummy fin is prepared in advance with the same dopant source layers and insulating buffer layers, enabling it to be selectively removed later without affecting the active regions. The etch process then selectively removes the dummy fin based on the exposed dopant source layer, achieving efficient removal and planarization.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables effective removal of dummy fins, improving the fin structure and process design, thereby enhancing the performance and efficiency of FinFETs by optimizing the contact area and reducing drain-induced barrier lowering and short-channel effects.

Implementation Method 1

solid state doping (SSD) technique to form a doped layer in the lower half of a fin structure

Methodology Applied
Scientific EffectSolid-state diffusion: Diffusion

Implementation Method 2

performing an etch process to cut the fin in the dummy region

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS10312353B2Semiconductor device and method for fabricating the same
Publication Date: 2019.06.04 UNITED MICROELECTRONICS CORP
  • US10312353B2 patent drawing
  • US10312353B2 patent drawing
  • US10312353B2 patent drawing

AI summary

A method for fabricating a semiconductor structure is provided in the present invention. The method includes the steps of forming a plurality of fins in a first region, a second region and a dummy region, forming a first solid-state dopant source layer and a first insulating buffer layer in the first region, forming a second solid-state dopant source layer and a second insulating buffer layer in the second region and the dummy region, and performing an etch process to cut the fin in the dummy region.