Dummy Fin Placement for FinFET Photo Resist Uniformity

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Solution Overview

Problem

The presence of empty regions near fin arrays in integrated circuits (ICs) can cause issues during photolithography processes, leading to uneven photo resist layers and potential process failures due to the formation of vertical fin structures in FinFETs.

Innovation Solution

The introduction of dummy fins in these empty regions to create an even topography, with a minimum spacing constraint to prevent interference with the fin arrays, and the use of grid maps to orderly place and expand dummy fin cells to minimize empty spaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If photolithography is performed over empty regions near fin arrays, then the photolithography process can be completed, but the photo resist layer becomes uneven causing focus issues and process failures

Engineering Contradiction:

Improvephotolithography process reliabilityVSAvoidphoto resist layer uniformity

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

Dummy fins are inserted into empty regions before the photolithography process to pre-establish a uniform topography. This preliminary action prevents the photo resist layer from becoming uneven during subsequent processing steps, thereby avoiding focus issues and process failures while maintaining manufacturing precision and reliability

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If empty regions are minimized by inserting dummy fins, then photo resist layer uniformity is improved, but the layout complexity and design constraints increase

Engineering Contradiction:

Improvephoto resist layer uniformityVSAvoidlayout complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

Dummy fins are strategically inserted only in empty regions adjacent to fin arrays where they are needed to ensure photo resist layer uniformity. The dummy fins are placed with specific spacing constraints (at least one pitch distance from active fins) to provide local topography correction without unnecessarily complicating the overall layout or interfering with active device regions

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS8869090B2Stretch dummy cell insertion in FinFET process

Publication Date: 2014.10.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method embodiment includes identifying an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins and outside a minimum spacing boundary, applying a grid map over the empty region, wherein the grid map comprises a plurality of grids inside the empty region, and filling the empty region with a plurality of dummy fin cells by placing a dummy fin cell in each of the plurality of grids, wherein applying the grid map and filling the empty region is performed using a computer.