FinFET Dummy Fin Layout for Uniform Fin Width and Profile

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Solution Overview

Problem

Existing FinFET devices face challenges in achieving uniformity in fin width and profile, particularly at the end of the fin, which complicates the fabrication process and affects the performance of FinFET devices.

Innovation Solution

A method for fabricating FinFET devices that involves forming dummy fins alongside active fins, where a patterned photoresist layer defines groups of dummy fins, allowing for selective etching to create open-spaces and shallow trench isolation regions, thereby ensuring consistent fin dimensions, profiles, and heights across the device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If selective etching of dummy fins is performed to create open-spaces, then fin width uniformity is improved, but process complexity increases

Engineering Contradiction:
Improvefin width uniformityVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Dummy fins are formed in advance alongside active fins during the same etching process. These dummy fins serve as placeholders that maintain uniform etching conditions and stress distribution across the substrate. The patterned photoresist layer is applied beforehand to define which dummy fins should be removed, enabling controlled creation of open-spaces that improve fin width uniformity while managing process complexity through pre-planned structuring.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Different regions of the substrate are treated differently through selective etching of dummy fins. Open-spaces are created at specific locations where dummy fins are removed, while other regions retain dummy fins for stress compensation. This local differentiation allows optimization of fin width uniformity in critical areas without unnecessarily complicating the entire process.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If dummy fins are formed alongside active fins, then fin profile uniformity is improved, but fabrication steps increase

Engineering Contradiction:
Improvefin profile uniformityVSAvoidfabrication steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The formation of dummy fins is merged with the active fin formation process. Both dummy fins and active fins are etched from the substrate simultaneously in the same etching step, using a single patterned photoresist layer. This combining of operations improves fin profile uniformity through consistent stress distribution while minimizing the increase in fabrication steps by integrating dummy fin creation into the existing process flow.

Inventive Principle:
Principle #5Merging (Combining)

3Stability of the object's composition

If open-spaces are created by removing dummy fins, then stress distribution is improved, but etching selectivity requirements increase

Engineering Contradiction:
Improvestress distributionVSAvoidetching selectivity
Core Design Contradiction:
Stability of the object's compositionVSManufacturing precision

Solution Approach 1:

A patterned photoresist layer serves as an intermediary that enables selective removal of dummy fins. The photoresist is applied and patterned to define specific regions where dummy fins should be removed to create open-spaces. This intermediary layer provides the necessary etching selectivity by protecting certain dummy fins while allowing removal of others, thereby achieving improved stress distribution without excessively stringent selectivity requirements on the etching process itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240347390A1Method of fabricating a finfet device
Publication Date: 2024.10.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240347390A1 patent drawing
  • US20240347390A1 patent drawing
  • US20240347390A1 patent drawing

AI summary

In an embodiment, a device includes a first active region over a substrate, a portion of the first active region having a first surface, the first surface defining a channel and being a first distance from the substrate. A dummy structure is adjacent to the first active region and has a sidewall extending from the substrate to a second surface facing way from the substrate, the second surface being a second distance, less than the first distance, from the substrate. An isolation region extends from a sidewall of a lower portion of the first active region over the second surface of the dummy semiconductor structure.