FinFET Dummy Gate Profile Etching to Prevent Short Circuits
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Solution Overview
Problem
The shrinking feature sizes in semiconductor devices, particularly in FinFETs, make it challenging to form reliable devices due to increased difficulties in fabrication processes, leading to issues such as short circuiting between fins and dummy gate electrodes.
Innovation Solution
The solution involves performing multiple etching operations on a gate electrode layer to form gate electrodes and dummy gate electrodes, with the etching process tuned to control the profile of the dummy gate electrode, resulting in a recessed lower portion that enlarges the spacing between fin terminals and the dummy gate electrode, thereby reducing short circuiting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes continue to decrease to increase device density, then higher device density is achieved, but fabrication reliability deteriorates due to increased difficulty in forming reliable FinFET devices
Solution Approach 1:
The etching process is segmented into multiple sequential operations (first etching operation, second etching operation, third etching operation) with different parameters and selectivities. Each operation targets specific features (gate electrodes, dummy gate electrodes, fin terminals) to achieve precise dimensional control and prevent short circuits while maintaining high device density
Solution Approach 2:
Different etching conditions are applied to different regions: the first etching operation uses high selectivity for gate electrode material to define gate electrodes and dummy gate electrodes; the second operation uses moderate selectivity to etch fin terminals; the third operation uses low selectivity to remove remaining dummy gate electrode material. This local differentiation ensures reliable feature formation at nanometer dimensions
2Ease of manufacture
If conventional single etching operation is used, then process simplicity is maintained, but short circuiting occurs between fin terminals and dummy gate electrodes
Solution Approach 1:
The etching process is divided into three distinct operations, each with specific selectivity ratios and duration controls. The first operation etches gate electrode material with high selectivity (10:1 to 50:1) to create gate electrodes and dummy gate electrodes. The second operation etches fin terminal material with moderate selectivity (5:1 to 10:1) to create spacing. The third operation removes dummy gate electrode material with low selectivity (1:1 to 5:1). This segmentation prevents short circuits by ensuring proper spacing and isolation
Solution Approach 2:
The first etching operation performs preliminary formation of gate electrodes and dummy gate electrodes with controlled dimensions and spacing. By establishing the dummy gate electrode structure early with proper spacing, subsequent operations can safely remove or modify these structures without causing short circuits between fin terminals
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or prevents short circuiting between fins and dummy gate electrodes, improving the yield and reliability of semiconductor devices by enlarging the spacing between the fin terminals and the dummy gate electrode.
Implementation Method 1
performing multiple etching operations on a gate electrode layer to form gate electrodes and dummy gate electrodes
Data Source
AI summary
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.