FinFET Dummy Gate Position Shift Mitigation via Insulation Layers
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Solution Overview
Problem
In FinFET semiconductor manufacturing, the position shift of dummy gate structures due to manufacturing deviations causes electrical leakage and distorts the epitaxially grown semiconductor materials, affecting the induced stress and charge carrier migration rate, leading to performance deterioration.
Innovation Solution
A method involving a substrate structure with fins and separation regions where insulation layers are carefully etched to maintain the horizontal level of the separation regions relative to the fins, preventing bridge formation between fins and dummy gate structures, and ensuring the integrity of epitaxially grown materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy gate structures are formed on STI to control CD uniformity, then the quality of FinFET is improved, but the position shift of dummy gate structures causes fins to bridge with dummy gate structures leading to electrical leakage
Solution Approach 1:
The patent applies preliminary action by forming the separation region and insulation layers before forming the dummy gate structures. This pre-established protective structure prevents fins from bridging with dummy gates even when position shifts occur during subsequent manufacturing processes, thereby maintaining both CD uniformity and preventing electrical leakage
Solution Approach 2:
The patent introduces an intermediary structure (separation region with insulation layers) between the fins and dummy gate structures. This intermediary layer acts as a protective barrier that prevents direct contact between fins and dummy gates, eliminating the electrical leakage problem while allowing the dummy gates to continue controlling CD uniformity
2Manufacturing precision
If dummy gate structures are formed on STI, then CD uniformity is controlled, but the position shift distorts the contour of epitaxially grown semiconductor materials affecting induced stress
Solution Approach 1:
The separation region and insulation layers are formed preliminarily before epitaxial growth. This pre-established protective structure maintains a stable reference plane that prevents position shifts during subsequent processes, thereby preserving both CD uniformity and the correct contour of epitaxially grown materials for proper stress induction
Solution Approach 2:
The insulation layers in the separation region serve as an intermediary that stabilizes the position reference. This intermediary structure prevents the dummy gate structures from shifting and distorting the epitaxially grown material contours, ensuring both CD uniformity and proper stress induction are maintained
3Stress or pressure
If the upper portion of fins neighboring dummy gate structures are etched to form dents, then stress is induced to channel, but the position shift of dummy gate structures lowers the migration rate of charge carriers
Solution Approach 1:
The separation region with insulation layers is formed preliminarily to establish a stable positional reference. This prevents dummy gate position shifts that would otherwise occur during subsequent processing, thereby maintaining both the induced stress in the channel and the migration rate of charge carriers
Solution Approach 2:
The insulation layers act as an intermediary that stabilizes the dummy gate position. By preventing position shifts, this intermediary structure ensures that the dents formed in the fins maintain their correct geometry and position, preserving both the stress induction function and the charge carrier migration rate
Data Source
AI summary
A semiconductor apparatus and its manufacturing method are presented. The method entails providing a substrate structure comprising a substrate, one or more fins positioned along a first direction on the substrate, and a separation region surrounding the fins. The separation region comprises a first separation region neighboring a first side of the fins and a second separation region neighboring a second side of the fins; forming a first and a second insulation layers on the substrate structure; forming a barrier layer; performing a first etching process using the barrier layer as a mask; removing the barrier layer; performing a second etching process using the remaining second insulation layer as a mask; forming a third insulation layer on side surfaces of the remaining first and second insulation layers; and performing a third etching process using the remaining second insulation layer and the third insulation layer as a mask.