FinFET Cell Isolation Using Dielectric Dummy Gates
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Solution Overview
Problem
FinFET fabrication methods face challenges in forming isolation structures that isolate neighboring circuit cells, leading to strain loss in silicon germanium fins and hinder scaling down capabilities due to the need for an additional gate cut process.
Innovation Solution
A FinFET cell design that incorporates dielectric dummy gates and plugs to provide electrical isolation between circuit cells without the additional gate cut process, maintaining strain in SiGe fins and enabling scaling down.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FinFET fabrication methods are used to form isolation structures, then neighboring circuit cells are isolated, but strain is lost in silicon germanium fins
Solution Approach 1:
The patent introduces dielectric dummy gates as intermediary structures between adjacent FinFET cells. These dummy gates act as mediators that provide electrical isolation through their dielectric material properties while physically occupying space that would otherwise require gate cut processes. The dummy gates maintain the strain in SiGe fins by eliminating the need for additional gate cut steps that would compromise the fin structure.
Solution Approach 2:
The patent segments the isolation function from the gate structure by introducing separate dielectric dummy gate elements between adjacent FinFET cells. This segmentation allows the isolation function to be performed by the dielectric material in the dummy gates while the actual gate structures remain intact and continuous, preserving strain in the SiGe fins without requiring gate cut operations.
2Reliability
If an additional gate cut process is used to form isolation structures, then neighboring circuit cells are isolated, but device complexity increases and scaling down is hindered
Solution Approach 1:
The patent merges the isolation structure formation with the existing gate patterning process. By forming dielectric dummy gates simultaneously with the gate structures during the same fabrication sequence, the isolation function is integrated into the standard FinFET manufacturing flow without requiring separate gate cut steps. This merging eliminates additional process complexity while achieving the required electrical isolation between adjacent circuit cells.
3Reliability
If conventional isolation structures are formed, then electrical isolation is achieved, but manufacturing precision is reduced due to additional process steps
Solution Approach 1:
The patent performs preliminary action by forming dielectric dummy gates during the standard gate patterning process, before any isolation structures would need to be created through gate cut operations. This preliminary formation of isolation elements using the existing gate mask and etch processes ensures that the SiGe fin structures are never subjected to additional cutting or damage, maintaining manufacturing precision and fin integrity throughout the fabrication sequence.
Data Source
AI summary
A semiconductor device includes: a substrate; a dielectric fin above the substrate and extending along a first direction; a gate electrode above the substrate and extending in a second direction that intersects the first direction; and a high-k dielectric layer over the gate electrode and over a top surface of the dielectric fin.