FinFET Dummy Gate Removal via Low-Pressure Dry Etching
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Solution Overview
Problem
Conventional planar FETs face issues such as sub-threshold swing degradation, significant drain-induced barrier lowering, and fluctuation of device characteristics when reduced in size, while FinFETs present manufacturing challenges as they are scaled down.
Innovation Solution
A method for removing polysilicon from over fins in FinFET transistors using a low-pressure, high-flow dry etching process followed by a wet etching process to recess the dummy gate material, which helps in controlling the thickness and preventing damage to underlying gate dielectrics, thereby improving the reliability and process window for FinFET manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If polysilicon is removed using conventional etching processes, then the dummy gate material can be removed, but the underlying gate dielectrics may be damaged and the process window is limited
Solution Approach 1:
The etching process is divided into multiple sequential steps: first a low-pressure, high-flow dry etching process to remove the majority of polysilicon, followed by a wet etching process to complete the removal. This segmentation allows each process to be optimized independently, achieving high precision removal while controlling damage to underlying dielectrics
Solution Approach 2:
The patent employs specific parameter changes in the etching process, including low pressure and high flow rate conditions for the dry etching step, followed by controlled wet etching. These parameter adjustments enable precise control over the etching rate and selectivity, removing polysilicon completely while preventing damage to the gate dielectrics
2Area of moving object
If FinFETs are scaled down to reduce device footprint, then device density increases, but manufacturing challenges and process complexity increase
Solution Approach 1:
The patent uses parameter changes in the etching process (low pressure, high flow rate, followed by wet etching) to enable precise removal of polysilicon in scaled-down FinFET structures. This controlled approach maintains manufacturing feasibility even as device dimensions are reduced for higher density
3Reliability
If low-pressure, high-flow dry etching is used to remove polysilicon, then negative loading effects are reduced and gate dielectrics are protected, but process time may increase
Solution Approach 1:
The etching process is segmented into two distinct phases: a low-pressure, high-flow dry etching phase that removes most polysilicon while protecting dielectrics, followed by a wet etching phase that completes the removal. This segmentation balances reliability protection with process efficiency
Solution Approach 2:
The patent extracts the harmful negative loading effects by using low-pressure, high-flow conditions that prevent polymer buildup and loading issues during polysilicon removal. This extraction of the problematic loading effect allows for faster, more reliable processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described method enhances the breakdown voltage and reliability of FinFETs by ensuring precise removal of dummy gate material, reducing negative loading effects and preventing damage to gate dielectrics, thus enabling more reliable and efficient semiconductor device production.
Implementation Method 1
A method for removing polysilicon from over fins in FinFET transistors using a low-pressure, high-flow dry etching process
Implementation Method 2
followed by a wet etching process to recess the dummy gate material
Data Source
AI summary
In accordance with some embodiments, conductive material is removed from over a first plurality of fins and second plurality of fins, wherein the first plurality of fins is located within a small gate length region and the second plurality of fins is located in a large gate length region. The removal is performed by initially performed a dry etch with a low pressure and a high flow rate of at least one etchant, which causes the conductive material to have a larger thickness over the second plurality of fins than over the first plurality of fins. As such, when a wet etch is utilized to remove a remainder of the conductive material, dielectric material between the second plurality of fins and the conductive material is not damaged.