FinFET Dummy Gate Surface Uniformity via Two-Stage Polishing

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Solution Overview

Problem

In the fabrication of fin field-effect transistors (FinFETs), the uneven surface of the dummy gate material layer due to the gate-last process leads to difficulties in controlling the thickness of the remaining dummy gate material, causing unevenness that affects subsequent processes.

Innovation Solution

A method involving the formation of a hard mask layer on the semiconductor fins, followed by a first dummy gate layer, polishing to expose the hard mask layer, removing the hard mask layer, and forming a second dummy gate layer to achieve a more even surface, allowing for uniform dummy gate formation and subsequent processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a dummy gate material layer is formed on fins and isolation structures with different surface heights, then the dummy gate layer fills the grooves between fins, but the surface of the dummy gate material layer becomes uneven, affecting subsequent processes

Engineering Contradiction:

Improvedummy gate formationVSAvoiddummy gate material layer surface uniformity

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The polishing process is divided into two distinct stages: a first polishing stage that removes the dummy gate material layer from isolation structures down to a reference plane, and a second polishing stage that selectively removes material from fin regions. This segmentation allows each stage to address specific surface uniformity requirements without interfering with the other.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A reference plane is established before the polishing process begins, serving as a predetermined stopping point for the first polishing stage. This preliminary establishment of a reference plane ensures that the polishing process has a clear target and prevents over-polishing, thereby maintaining manufacturing precision.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If the surface of the dummy gate material layer is uneven, then subsequent fabrication processes are affected, but adding more polishing steps increases process complexity

Engineering Contradiction:

Improvesurface uniformity for subsequent processesVSAvoidfabrication process steps

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The polishing process is designed to achieve multiple objectives simultaneously: leveling the surface for uniformity, controlling the remaining thickness through the stop layer, and preparing the surface for subsequent fabrication steps. This multi-functionality reduces the need for additional separate process steps.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The two-stage polishing process operates continuously without requiring intermediate handling or repositioning of the substrate. The transition between stages is seamless, maintaining continuous useful action that improves efficiency while achieving the required surface uniformity.

Inventive Principle:

Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a more even surface of the dummy gate material layer, ensuring uniformity and consistency in the FinFET fabrication process, enhancing the reliability and performance of the transistors.

Implementation Method 1

polishing the first dummy gate layer until the hard mask layer is exposed

Methodology Applied

Scientific EffectChemical Mechanical Polishing:

Implementation Method 2

etching the second dummy gate layer and the first dummy gate layer to form a dummy gate on each of the fins

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS9117906B2Fin field-effect transistors and fabrication method thereof

Publication Date: 2015.08.25 SEMICON MFG INT CORP

AI summary

A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate, and forming a plurality of fins with hard mask layers and an isolation structure. The process also includes forming a first dummy gate layer on the fins and the isolation structure, and polishing the first dummy gate layer until the hard mask layer is exposed. Further, the method includes removing the hard mask layer to expose a top surface of the fins, and forming a second dummy gate material layer on the first dummy gate material layer. Further, the method also includes etching the second dummy gate layer and the first dummy gate layer to form a dummy gate on each of the fins.