FinFET Dummy Gate Profile to Prevent Critical Dimension Loss
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Solution Overview
Problem
Existing technologies for forming Fin Field-Effect Transistor (FinFET) devices face issues with undesirable lateral etching at the bottom portions of dummy gate structures, leading to reduced critical dimensions due to high and less controllable etching rates, especially in areas with varying transistor densities.
Innovation Solution
The method involves patterning blanket dummy gate structures with different profiles in dense and sparse areas, using intermediate dummy gates with specific recess angles to ensure that adjacent dummy gate structures have tip edges pointing towards each other, maintaining the critical dimensions of active gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If blanket dummy gate structures are patterned in areas with varying transistor densities, then the critical dimensions of active gate structures are reduced due to lateral etching at the bottom portions of dummy gate structures, but uniform patterning across different density areas is difficult to achieve
Solution Approach 1:
The patent applies local quality by forming intermediate dummy gates with different profiles in different areas: in sparse areas, intermediate dummy gates have recesses with varying angles to prevent lateral etching, while in dense areas, standard dummy gate structures are used. This localized adaptation ensures that each area's specific density requirements are met, preventing critical dimension reduction in sparse areas while maintaining patterning uniformity across the entire substrate.
Solution Approach 2:
The substrate is segmented into different areas based on transistor density (sparse areas vs. dense areas), and different intermediate dummy gate structures are formed in each segment. This segmentation allows the patterning process to be optimized for each specific area, with sparse areas receiving additional protection through varying angle recesses and dense areas using standard structures, thereby resolving the contradiction between maintaining critical dimensions and achieving uniform patterning.
2Manufacturing precision
If standard dummy gate structures are used in sparse areas, then lateral etching occurs at the bottom portions leading to reduced critical dimensions, but adding complex structures increases device complexity
Solution Approach 1:
Instead of applying a complex uniform structure across the entire substrate, the patent uses local quality by forming varying angle recesses only in sparse areas where lateral etching is a problem. The recess angle varies locally based on the specific area's needs, providing targeted protection against lateral etching without unnecessarily complicating structures in dense areas, thus balancing manufacturing precision with device complexity.
3Productivity
If etching rate is increased to improve productivity, then lateral etching at dummy gate bottoms increases reducing critical dimensions, but slower etching maintains precision
Solution Approach 1:
The patent applies preliminary anti-action by forming intermediate dummy gates with varying angle recesses before the final etching step. These pre-formed structures act as protective elements that counteract the lateral etching that would otherwise occur during high-speed etching. The varying angles are specifically designed to prevent etchant access to the bottom portions of dummy gates, allowing high productivity etching rates to be maintained without sacrificing critical dimension precision.
Data Source
AI summary
A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.