FinFET Dummy Gate Spacer Alignment for Contact Plug Accuracy
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Solution Overview
Problem
The short-channel effect in MOSFETs leads to decreased threshold voltage, increased power consumption, and reduced signal-to-noise ratio, which existing improvements such as doping, stress enhancement, and reduced gate oxide thickness cannot adequately address as the channel size shrinks, and the alignment of contact plugs in FinFETs becomes increasingly inaccurate, causing short circuits and parasitic overlap capacitance.
Innovation Solution
A method for manufacturing Fin Field-Effect Transistors involving the formation of a dummy gate and spacer to create self-aligned gate and source/drain regions, ensuring equal heights and accurate alignment of contact plugs, thereby improving AC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel size is reduced to increase integration level, then the operating current and density increase, but the short-channel effect becomes more significant causing threshold voltage degradation and increased power consumption
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective channel area and operating current while maintaining short channel length, thereby improving integration level without sacrificing threshold voltage control.
Solution Approach 2:
The channel is segmented into multiple vertical fins rather than a single planar channel. This segmentation increases the total channel area and current capacity while each individual fin maintains good electrostatic control, resolving the contradiction between high integration and threshold voltage stability.
2Ease of manufacture
If conventional FinFET manufacturing is used, then the device structure is formed, but the contact plug alignment becomes inaccurate causing short circuits and parasitic overlap capacitance
Solution Approach 1:
A dummy gate structure is formed preliminarily during the manufacturing process. This dummy gate serves as a reference structure that enables accurate alignment of subsequent contact plugs, preventing alignment errors and parasitic capacitance while maintaining ease of FinFET structure formation.
Solution Approach 2:
The dummy gate acts as an intermediary reference structure between the FinFET formation process and the contact plug alignment process. It mediates the alignment accuracy issue by providing a physical reference that ensures precise contact plug positioning without complicating the overall manufacturing process.
Data Source
AI summary
Embodiments of the present invention disclose a method for manufacturing a Fin Field-Effect Transistor. When a fin is formed, a dummy gate across the fin is formed on the fin, a spacer is formed on sidewalls of the dummy gate, and a cover layer is formed on the first dielectric layer and on the fin outside the dummy gate and the spacer; then, an self-aligned and elevated source/drain region is formed at both sides of the dummy gate by the spacer, wherein the upper surfaces of the gate and the source/drain region are in the same plane. The upper surfaces of the gate and the source/drain region are in the same plane, making alignment of the contact plug easier; and the gate and the source/drain region are separated by the spacer, thereby improving alignment accuracy, solving inaccurate alignment of the contact plug, and improving device AC performance.