FinFET Dummy Structure for Uniform Pattern Density
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Solution Overview
Problem
The existing FinFET semiconductor devices face challenges in achieving even local pattern density and preventing dishing problems due to height differences between dummy stacks and gate structures, leading to defects from uneven forces in subsequent processes.
Innovation Solution
A semiconductor device and method that includes a substrate with a semiconductor fin divided by an isolation structure into sub-fins, where a dummy structure is formed on the isolation structure, laterally extending to overlap portions of both sub-fins, ensuring the top surfaces form a plane and the dummy and gate structures have identical heights, allowing for even pattern density and mitigating dishing issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy stacks are formed on insulation structures to provide even local pattern density, then pattern density uniformity is improved, but height difference between dummy stacks and gate structures causes dishing problems and defects
Solution Approach 1:
The dummy structure is merged with the gate structure by forming both on the same fin structure and at the same height, eliminating the height difference that caused dishing problems while maintaining the pattern density uniformity benefit
Solution Approach 2:
The dummy structure and gate structure are formed at the same height level (equipotential surface), ensuring that subsequent planarization processes experience uniform forces across the entire structure, preventing dishing defects
2Adaptability or versatility
If gate structures are formed on vertical fins with different device pattern density, then device functionality is achieved, but topography becomes uneven leading to dishing problems
Solution Approach 1:
The dummy structure is locally positioned on the fin structure between adjacent gate structures, providing enhanced pattern density in specific regions while maintaining overall surface uniformity through its height-matching design
Data Source
AI summary
A method for fabricating a semiconductor device comprises: Firstly, a semiconductor fin comprising a first sub-fin and a second sub-fin protruding from a surface of a substrate is provided. An isolation structure having an opening extending therein is then provided in the semiconductor fin to electrically isolate the first sub-fin and the second sub-fin. Subsequently, a first dummy structure disposed on the first isolation structure and having at least one metal layer entirely overlapping on the first isolation structure along a long axis of the semiconductor fin is formed, wherein the metal layer laterally conformally extends downwards into the opening and extends upwards beyond the first isolation structure along the long axis of the semiconductor fin, so as to form a stepped structure overlapping on sidewalls and a bottom of the opening, a portion of the first sub-fin and a portion of the second sub-fin.