FinFET Gate Stack Dummy Pillars for CMP Thickness Control
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling the thickness of metal gates during the chemical mechanical polishing (CMP) process, leading to defects such as convex or concave surfaces, which can cause mismatches between devices and contacts, affecting the integrity of semiconductor devices like FinFETs.
Innovation Solution
The implementation of dummy pillars in the gate stacks, which are formed to be coplanar with the gate stacks, helps in controlling the metal gate thickness and reducing defects, ensuring better contact landing and vertical profile for improved N/P boundary metal topography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chemical mechanical polishing (CMP) process is used to manufacture metal gates, then manufacturing productivity is improved, but manufacturing precision deteriorates due to uncontrolled metal gate thickness leading to convex or concave surfaces
Solution Approach 1:
The patent applies preliminary action by forming dummy pillars before the CMP process to establish a predetermined topography that guides the polishing process. The dummy pillars are formed at specific locations to create a template that ensures uniform metal gate thickness during subsequent deposition and polishing steps, preventing convex or concave surface defects while maintaining manufacturing efficiency
2Manufacturing precision
If dummy pillars are added to control metal gate thickness, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The dummy pillars serve as intermediary structures that facilitate precise metal gate thickness control without becoming part of the final functional device. These temporary structures mediate between the manufacturing process requirements and the final device topology, enabling precise CMP polishing while being removed or integrated in a way that does not compromise the functional simplicity of the FinFET device
3Ease of manufacture
If metal gate thickness is not controlled properly, then manufacturing ease is improved, but reliability deteriorates due to mismatches between devices and contacts
Solution Approach 1:
The patent implements feedback by using the dummy pillar topography as a reference standard that provides real-time guidance during the CMP process. The predetermined locations and heights of the dummy pillars create a feedback mechanism that ensures the metal gate thickness is uniformly controlled, preventing mismatches at device-contact interfaces and ensuring reliable electrical connections while maintaining ease of manufacture
Data Source
AI summary
A semiconductor structure includes a substrate with fin features extending along a first direction; a plurality of gate stacks and a plurality of dummy pillars. The gate stacks are deposited over the substrate and extend along a second direction different from the first direction to cover the sidewalls and top surfaces of the fin features exposed from the substrate. Each gate stack includes a first gate region, a second gate region and a central region formed between the first gate region and the second gate region without covering the fin features. The dummy pillars are formed in the gate stacks besides the fin features and/or on the fin features.