FinFET Dummy Structure Layout for Scaled MOSFET Reliability
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Solution Overview
Problem
The scaling down of metal oxide semiconductor field effect transistors (MOSFETs) in semiconductor devices leads to deteriorated operating characteristics, necessitating improvements in device integration and performance.
Innovation Solution
Incorporation of a dummy structure with specific line and connection parts between fin patterns and gate electrodes, featuring varying distances between connection parts to enhance electrical properties and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MOSFET size is scaled down to increase integration, then device integration is improved, but operating characteristics deteriorate
Solution Approach 1:
The patent introduces dummy structures that replicate the geometric characteristics of actual transistor gates without providing electrical function. These dummy gates copy the shape and positioning of real gates to maintain consistent electrical field distribution and stress conditions across the semiconductor device, thereby preserving operating characteristics while enabling higher integration.
Solution Approach 2:
The patent applies different structural configurations locally - actual transistor structures in active regions and dummy structures in non-active regions. The dummy structures are specifically designed with matching geometric properties only in the regions where they are placed, allowing local optimization of electrical characteristics without affecting overall device integration.
2Reliability
If dummy structure is added to improve electrical properties, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the formation of dummy structures with existing manufacturing processes by using the same gate patterning and deposition steps. The dummy structures are created simultaneously with actual transistor gates through unified process flows, eliminating the need for separate fabrication steps and reducing overall device complexity despite the addition of dummy elements.
Data Source
AI summary
A semiconductor device may include a first fin pattern, a first source/drain pattern on the first fin pattern, a second fin pattern spaced apart in a first direction from the first fin pattern, a second source/drain pattern on the second fin pattern, a first gate electrode overlapping the first fin pattern and extending in a second direction crossing the first direction, a second gate electrode overlapping the second fin pattern and extending in the second direction, and a first dummy structure between the first fin pattern and the second fin pattern and between the first gate electrode and the second gate electrode. The first dummy structure may include first to third line parts extending in the second direction, first and second connection parts connecting the first and second line parts to each other, and a third connection part connecting the second and third line parts to each other.