FinFETs with Same Physical Gate Length and Different Effective Channel Lengths
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Solution Overview
Problem
Conventional finFET semiconductor devices face challenges in achieving multiple effective channel lengths without increasing physical gate length or contact resistance, which affects off-state current and on-state drive current performance.
Innovation Solution
The solution involves forming finFET structures with the same physical gate length but different effective channel lengths by varying the fin recess profiles and in-situ doped source/drain epitaxy profiles, allowing for both longer and shorter effective channel lengths to be achieved without altering the physical gate length or contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the effective channel length is increased to reduce off-state current, then the off-state current decreases, but the on-state drive current also decreases
Solution Approach 1:
The patent applies local quality by creating different fin recess profiles in different regions of the semiconductor device. Specifically, a first fin recess profile is formed in a first region to achieve a first effective channel length, while a second fin recess profile is formed in a second region to achieve a second effective channel length. This allows different local regions to have optimized channel lengths tailored to their specific functional requirements, enabling simultaneous optimization of off-state current in one region and on-state drive current in another region.
2Length of stationary object
If the physical gate length is increased to achieve longer effective channel length, then the effective channel length increases, but the device area and contact resistance increase
Solution Approach 1:
The patent applies dimensionality change by transitioning from a planar gate structure to a three-dimensional FinFET structure with vertical fins extending from the substrate. The gate electrode wraps around the fin structure, creating a multi-dimensional control geometry. This allows the effective channel length to be controlled by the horizontal gate length while the vertical fin height provides an additional dimensional parameter to optimize device performance without proportionally increasing the planar device area.
Solution Approach 2:
The patent applies segmentation by dividing the semiconductor device into multiple regions with different fin recess profiles. Each region can be independently optimized for specific performance characteristics. This segmentation allows the device to achieve multiple effective channel lengths within the same physical gate length, effectively decoupling the relationship between physical gate length and effective channel length.
3Adaptability or versatility
If different effective channel lengths are achieved by varying physical gate lengths, then the effective channel lengths differ, but the device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent applies parameter changes by modifying the fin recess profile parameters (depth, width, shape) rather than changing the physical gate length to achieve different effective channel lengths. By controlling the extent and geometry of the fin recesses, the effective channel length can be adjusted independently of the physical gate dimensions. This parameter-based approach allows for versatile device design while maintaining uniform physical gate structures that simplify manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of finFETs with lower off-state current and higher on-state drive current characteristics while maintaining similar contact resistance, addressing the need for varied channel lengths in semiconductor devices.
Implementation Method 1
The source and drain regions 130, 140 may be formed by removing semiconductor material on sides of the channel region 120 by a recess etch and epitaxially regrowing the source region 130 and the drain region 140 in the recessed regions on opposing sides of the channel region 120.
Data Source
AI summary
A semiconductor structure includes a first finFET device including a first fin, a first gate electrode structure on sidewalls and an upper surface of the first fin, a first channel region beneath the first gate electrode structure, and first source and drain regions in the first fin on opposite sides of the first channel region, and a second finFET device including a second fin, a second gate electrode structure on sidewalls and an upper surface of the second fin, a second channel region beneath the second gate electrode structure, and second source and drain regions in the second fin on opposite sides of the second channel region. The second gate electrode structure has a second physical gate length that is substantially the same as a first physical gate length of the first gate electrode structure, and the second finFET device has a second effective channel length that is different from a first effective channel length of the first gate electrode structure.