FinFET Source-Drain Electrode Protection via Covering Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
During the fabrication of Fin-FET devices, the etching process to remove dummy insulating layers can lead to lateral etching of silicon oxides, causing gaps that expose source and drain electrodes, which can result in unreliable connections with the metal gate electrode, degrading the device's reliability.
Innovation Solution
A method involving the formation of a covering layer with a sacrificial layer on the dummy gate structures, using these layers as an etch mask to create trenches for source and drain electrodes, followed by an interlayer dielectric layer and planarization to ensure the electrodes are far enough from the dummy gate structure, preventing lateral etching exposure and subsequent metal gate connection issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching process is used to remove the dummy insulating layer, then the dummy gate electrode and dummy insulating layer can be removed to form a trench for metal gate electrode formation, but the etching process causes lateral etching of silicon oxides in the shallow trench isolation, forming gaps that expose the source electrode and/or drain electrode
Solution Approach 1:
A covering layer is introduced as an intermediary protective structure between the etching process and the shallow trench isolation silicon oxides. This covering layer prevents direct contact between the etching chemistry and the isolation layer, thereby preventing lateral etching and gap formation that would expose the source and drain electrodes. The covering layer serves as a mediator that allows the necessary etching to proceed while protecting against harmful side effects.
Solution Approach 2:
The covering layer is formed prior to the etching process as a preventive measure. By establishing this protective barrier in advance, the patent prevents the lateral etching issue from occurring in the first place, rather than attempting to correct it afterward. This preliminary protective action ensures that the source and drain electrodes remain covered and protected throughout the subsequent processing steps.
2Ease of manufacture
If the dummy gate electrode and dummy insulating layer are removed to form a trench, then the metal gate electrode can be formed, but the source electrode and drain electrode may be exposed due to lateral etching
Solution Approach 1:
The covering layer serves as a protective intermediary that remains in place during the removal of the dummy gate electrode and dummy insulating layer. This intermediary structure prevents the etching process from laterally attacking the shallow trench isolation and exposing the source and drain electrodes. The covering layer is specifically designed to withstand the etching conditions while protecting the underlying structures.
Solution Approach 2:
The covering layer is formed in advance before the dummy gate and insulating layer removal process. This preliminary protective measure ensures that when the dummy structures are removed to allow metal gate formation, the source and drain electrodes remain protected from exposure. The advance preparation of this protective layer simplifies the overall manufacturing process by preventing defects rather than requiring additional corrective steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the semiconductor device by maintaining the electrodes' distance from the trench formed by removing the dummy gate and insulating layer, preventing metal gate connection and improving the stress distribution from source and drain electrodes to the channel, thus enhancing device performance.
Implementation Method 1
during the etching process to remove the dummy insulating layer, the etching process may result in lateral etching of silicon oxides in the shallow trench isolation (STI)
Data Source
AI summary
A semiconductor device includes a semiconductor substrate; a plurality of semiconductor fin structures formed on the semiconductor substrate; a plurality of gate structures, each formed on a semiconductor fin structure; a source electrode and a drain electrode formed on two opposite sides of each gate structure, wherein, at least a portion of the source electrode and at least a portion of the drain electrode are formed in the semiconductor fin structure; a covering layer formed on the semiconductor fin structures and also on two side surfaces of each gate structure; and an interlayer dielectric layer formed on the covering layer, wherein the interlayer dielectric layer covers each source electrode and each drain electrode, a trench is formed in the interlayer dielectric layer to expose a portion of each semiconductor fin structure, and a gate structure is formed in each trench.