FinFET Elevated Source Drain Structure Reducing GIDL
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Solution Overview
Problem
Conventional FinFETs face issues with higher off current and Gate-Induced Leakage (GIDL) due to shorter effective length between source and drain, which worsens with reduced transistor sizes.
Innovation Solution
An elevated source/drain structure is implemented, featuring a recessed region between source and drain pairs with a gate structure perpendicular to the active fin, increasing the effective length and reducing GIDL and off current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the channel length is reduced to increase integration density, then the device size is reduced, but the off current and GIDL increase
Solution Approach 1:
The gate structure is positioned vertically above the channel region, extending in the vertical dimension rather than only laterally. This three-dimensional gate configuration increases the effective gate control area over the channel, allowing for better suppression of off current and GIDL while maintaining a compact lateral footprint for high integration density.
Solution Approach 2:
The gate structure is specifically positioned to overlap with the channel region in the center area between source and drain pairs. This localized positioning optimizes the electric field distribution precisely where needed to control carrier flow, improving threshold voltage control and reducing leakage currents in the critical channel region.
2Length of moving object
If the effective length between source and drain is reduced, then the device area is reduced, but the GIDL and off current increase
Solution Approach 1:
The gate structure extends vertically above the channel, adding a vertical dimension to the effective gate length. This allows the gate to exert control over a longer effective distance between source and drain without increasing the lateral device footprint, thereby reducing GIDL and off current while maintaining compact device area.
Solution Approach 2:
The gate structure comprises a gate electrode and a gate spacer formed in a recessed region, creating a composite structure that optimizes both electrical control and physical space utilization. The gate spacer extends the effective gate control region, increasing the effective length between source and drain to reduce leakage currents.
3Area of moving object
If the channel width is decreased to reduce device size, then the integration density increases, but the threshold voltage increases
Solution Approach 1:
The gate structure is positioned to overlap specifically with the channel region in the center area between source and drain pairs. This localized positioning creates a concentrated electric field in the channel region, providing strong control over the threshold voltage even when the channel width is reduced, thereby maintaining reliable device operation at scaled dimensions.
Data Source
AI summary
Example embodiments are directed to a method of forming a field effect transistor (FET) and a field effect transistor (FET) including a source/drain pair that is elevated with respect to the corresponding gate structure.