FinFET Epi Growth Uniformity via Segmented Spacer Etching

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Solution Overview

Problem

The formation of epi semiconductor material on FinFET devices is challenging due to variations in fin spacer height and asymmetry, leading to non-uniform epi material growth, which can result in electrical shorts, increased contact resistance, and reduced device performance.

Innovation Solution

A method involving the formation of a fin spacer adjacent to a recessed layer of insulating material, followed by the deposition of a conformal layer of a second spacer material, and subsequent etching processes to expose the fin sidewalls and upper surface, allowing for uniform epi semiconductor material growth on the source/drain regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If fin spacer height is reduced to limit epi material width, then electrical shorts are prevented, but contact resistance increases

Engineering Contradiction:
Improveelectrical shortsVSAvoidcontact resistance
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent divides the fin structure into multiple segments by forming separate epi material regions on different portions of the fin. The first epi material is formed on the first portion of the fin, and the second epi material is formed on the second portion of the fin, creating segmented epi regions that can be independently controlled for optimal electrical performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different treatments to different portions of the fin structure. The first epi material and second epi material are formed with different characteristics on different portions of the fin, allowing local optimization of electrical properties - one region optimized for preventing shorts while another optimized for minimizing contact resistance

Inventive Principle:
Principle #3Local quality

2Reliability

If epi material volume is increased to reduce contact resistance, then device performance improves, but epi material merging occurs causing electrical shorts

Engineering Contradiction:
Improvecontact resistanceVSAvoidelectrical shorts
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The fin structure is divided into multiple portions with separate epi material formations. The first epi material is formed on the first portion and the second epi material on the second portion, creating physically separated epi regions that prevent merging while maintaining sufficient volume for low contact resistance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary structure or process step between epi material formations that prevents direct merging. The separate formation processes and spatial separation act as intermediaries that allow each epi material to grow to optimal volume without coalescing into short-circuiting structures

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If fin pitch is reduced to increase device density, then integration density improves, but epi material uniformity across fins becomes difficult to maintain

Engineering Contradiction:
Improvedevice densityVSAvoidepi material uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent segments the epi material formation process into distinct steps for different fin portions. By forming first epi material on first portions and second epi material on second portions separately, the process can maintain uniformity control even as fin pitch decreases and fins become more densely packed

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions to prepare the fin structure before epi material formation. Fin spacers are formed at specific heights to pre-establish uniform exposure conditions, and surface preparations are made in advance to ensure consistent epi material growth across all fins before the actual epi deposition begins

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures the formation of uniformly sized epi semiconductor material, reducing the risk of electrical shorts and improving contact resistance, thereby enhancing device performance and reliability.

Implementation Method 1

performing an etching process to remove the second conformal layer of the second spacer material from above the fin spacer and thereby re-expose the sidewalls of the fin located above an upper surface of the fin spacer and the upper surface of the fin

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

forming an epi semiconductor material on the exposed sidewalls and upper surface of the fin above the fin spacer

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS9887094B1Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device
Publication Date: 2018.02.06 GLOBALFOUNDRIES US INC
  • US9887094B1 patent drawing
  • US9887094B1 patent drawing
  • US9887094B1 patent drawing

AI summary

One illustrative method disclosed includes, among other things, forming a fin spacer adjacent a lower portion of a fin that is comprised of a fin spacer material, forming a conformal layer of a second spacer material on the exposed sidewalls and the upper surface of the fin, on the fin spacer and adjacent a gate structure of the FinFET device, wherein the second spacer material is a different material than the fin spacer material, performing an etching process to remove the second conformal layer from above the fin spacer to thereby re-expose the sidewalls of the fin above the fin spacer and the upper surface of the fin while forming a gate spacer comprising the second spacer material adjacent the gate structure, and forming an epi semiconductor material on the exposed sidewalls and upper surface of the fins above the first fin spacer.