FinFET Source/Drain Epi Layer Placement for Short Channel Control
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Solution Overview
Problem
In FinFET devices, the short channel effect and hot carrier injection lead to degraded performance and reduced device lifespan due to the proximity of source and drain regions, which affects the threshold voltage and switching characteristics.
Innovation Solution
The method involves forming a FinFET device with a fin in a semiconductor substrate, a first recessed layer of insulating material, and epi semiconductor material on the fin, followed by a second recessed layer of insulating material with a source/drain contact structure conductively coupled to the epi semiconductor material, optimizing the placement and thickness of the epi semiconductor material to reduce the impact of the short channel effect and hot carrier injection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of planar FETs is significantly decreased to improve switching speed and lower operation currents and voltages, then the switching speed is improved and operation currents and voltages are lowered, but the separation between source and drain regions decreases making it difficult to prevent short channel effects
Solution Approach 1:
The patent transitions from planar FET to FinFET architecture, moving the channel from a two-dimensional plane to a three-dimensional vertical fin structure. This dimensional change allows the channel to be controlled by a gate that wraps around three sides of the fin, providing superior electrostatic control and preventing short channel effects even when the channel length is reduced, thereby enabling faster switching speeds without sacrificing reliability
2Speed
If epi semiconductor material is formed on the portions of the fin positioned in the source/drain regions to improve device performance, then the switching speed is enhanced, but off-state leakage currents increase
Solution Approach 1:
The patent applies different material compositions to different regions of the FinFET structure. Specifically, silicon germanium (SiGe) is used in the source and drain regions while the channel region maintains pure silicon composition. This local differentiation allows the source/drain regions to provide high carrier concentration for fast switching, while the pure silicon channel maintains low off-state leakage currents by preventing carrier generation in the critical conduction path
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the switching speed and reduces off-state leakage currents, improving the reliability and performance of FinFET devices by effectively managing the source/drain regions and mitigating the short channel effect and hot carrier injection.
Implementation Method 1
epi semiconductor material is formed on the portions of the fin positioned in the source/drain regions of the device
Data Source
AI summary
One illustrative method disclosed herein includes forming at least one fin, forming a first recessed layer of insulating material adjacent the at least one fin and forming epi semiconductor material on the at least one fin. In this example, the method also includes forming a second recessed layer of insulating material above the first recessed layer of insulating material, wherein at least a portion of the epi semiconductor material is positioned above a level of the upper surface of the second recessed layer of insulating material, and forming a source/drain contact structure above the second recessed layer of insulating material, wherein the source/drain contact structure is conductively coupled to the epi semiconductor material.