FinFET Epitaxial Layer Contact Structure for Parasitic Capacitance Reduction
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Solution Overview
Problem
The performance of conventional FinFET semiconductor structures is poor due to parasitic capacitance and increased contact resistance, which affects power consumption and current flow, primarily caused by the formation of conductive structures on epitaxial layers and isolation layers with height differences.
Innovation Solution
A semiconductor structure and method involving the formation of a third epitaxial layer between first and second regions, with the third epitaxial layer in contact with both, and a conductive structure formed on these epitaxial layers to reduce parasitic capacitance and increase contact area, thereby improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conductive structures are formed on epitaxial layers and isolation layers with height differences, then multi-layer metal wire interconnection is achieved, but parasitic capacitance increases and contact resistance increases
Solution Approach 1:
The patent introduces a third epitaxial layer in the middle region between first and second epitaxial layers, creating a new dimensional level for contact formation. This allows conductive structures to contact three epitaxial layers simultaneously, transforming the conventional two-point contact into a multi-level contact structure that reduces parasitic capacitance and contact resistance while achieving multi-layer metal wire interconnection
2Adaptability or versatility
If conventional FinFET structure is used, then transistor basic function is achieved, but performance is poor due to parasitic capacitance and contact resistance
Solution Approach 1:
The patent segments the contact structure into multiple independent epitaxial layers (first, second, and third epitaxial layers) positioned at different locations. Each epitaxial layer can be independently optimized and contacted by conductive structures, allowing the transistor to maintain basic function while significantly reducing parasitic capacitance and improving power efficiency through distributed contact architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and contact resistance, enhancing the overall performance of the semiconductor structure by increasing the contact area between the conductive structure and the epitaxial layers, leading to improved power efficiency and current flow.
Implementation Method 1
a first epitaxial layer formed on the first fin, a second epitaxial layer formed on the second fin, and a third epitaxial layer formed on the third fin
Data Source
AI summary
A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate, which includes a first region, a second region, and a third region. The semiconductor structure also includes a first fin, a second fin, and a third fin formed on the first, second, and third regions, respectively. Moreover, the semiconductor structure includes an isolation layer formed on the substrate, and a portion of sidewall surface of each of the first, second, and third fins. In addition, the semiconductor structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer formed on the first, second, and third fins, respectively. Two sides of the third epitaxial layer are in contact with the first epitaxial layer and the second epitaxial layer, respectively. Further, the semiconductor structure includes a conductive structure formed on the first, second, and third epitaxial layers.