FinFET Semiconductor Device With Epitaxial Fin Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current planar FETs fail to meet the requirements of miniaturized electronic products due to increased drain-induced barrier lowering and short channel effects, necessitating the development of non-planar FinFETs with a three-dimensional channel structure to enhance performance and integration.
Innovation Solution
A FinFET semiconductor device with a fine lattice structure is formed using a substrate with shallow trench isolations, a semiconductor layer, and fin structures embedded in sub-recesses, eliminating the need for a fin cut process and utilizing epitaxial growth for buffer layers to achieve good lattice properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar FET structure is used, then manufacturing process is simple, but drain-induced barrier lowering and short channel effects increase
Solution Approach 1:
The patent transitions from a planar FET structure to a FinFET structure by introducing a three-dimensional channel with vertical fins. This dimensional change increases the gate-channel overlapping area, improving channel control and reducing drain-induced barrier lowering and short channel effects while maintaining compatibility with traditional manufacturing processes
2Reliability
If FinFET structure is adopted, then channel control is improved, but device complexity increases
Solution Approach 1:
The channel region is segmented into multiple vertical fins, creating a three-dimensional structure that increases gate-channel overlapping area. This segmentation improves channel control effectiveness while the fins are formed using standard epitaxial growth and etching processes, managing the complexity through established manufacturing techniques
3Productivity
If miniaturization is pursued, then integration density increases, but lattice structure quality deteriorates
Solution Approach 1:
A buffer layer is formed preliminarily before the channel layer to compensate for lattice mismatch. This preliminary action prevents lattice structure deterioration during miniaturization, enabling high integration density while maintaining manufacturing precision through proactive lattice matching
4Manufacturing precision
If additional fin cut process is added, then fin structure precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent extracts or removes the additional fin cut process from the manufacturing sequence. Fin structures are formed directly through epitaxial growth and selective etching without requiring separate fin cutting steps, thereby maintaining fin structure precision while reducing manufacturing complexity and process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces drain-induced barrier lowering and short channel effects, increasing current between the source and drain, while maintaining compatibility with traditional logic device processes and achieving smaller scales without additional processing steps.
Implementation Method 1
utilizing epitaxial growth for buffer layers to achieve good lattice properties
Data Source
AI summary
The present invention provides a semiconductor device, including a substrate, a first semiconductor layer, a plurality of first sub recess, a plurality of insulation structures and a first top semiconductor layer. The substrate has a first region disposed within an STI. The first semiconductor layer is disposed in the first region. The first sub recesses are disposed in the first semiconductor layer. The insulation structures are disposed on the first semiconductor layer. The first top semiconductor layer forms a plurality of fin structures, which are embedded in the first sub recesses, arranged alternatively with the insulation structures and protruding over the insulation structures.