FinFET Epitaxial Isolation Maintaining Uniaxial Strain

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Solution Overview

Problem

In FinFET devices, cutting fins during fabrication relaxes compressive strain, degrading performance, especially for p-type FETs that benefit from compressive strain, as it disrupts the uniaxial strain necessary for optimal performance.

Innovation Solution

Epitaxially growing p-type and n-type doped regions between gate electrodes of adjacent transistors to create back-to-back P-N junctions, thereby electrically isolating them without cutting the fins, maintaining uniaxial strain and preserving device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fins are cut to isolate adjacent transistors, then electrical isolation between transistors is achieved, but uniaxial strain is disrupted

Engineering Contradiction:
Improveelectrical isolation between transistorsVSAvoiduniaxial strain
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent applies different doping types (p-type or n-type) to epitaxial regions based on the specific location and transistor type. This local customization ensures that compressive strain is restored in p-type FETs while maintaining appropriate strain characteristics in n-type FETs, preserving uniaxial strain stability locally throughout the device.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent creates a composite structure combining the original fin material with epitaxially grown regions of different doping types and compositions. This composite structure maintains both electrical isolation and uniaxial strain by integrating materials with complementary properties.

Inventive Principle:
Principle #40Composite materials

2Reliability

If epitaxial regions are grown to maintain strain, then device performance is enhanced, but manufacturing process complexity increases

Engineering Contradiction:
Improvedevice performanceVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs epitaxial region growth during the source/drain formation step, which is an early stage in the fabrication process. By establishing the strain structure early, subsequent processing steps can proceed without additional strain-related operations, reducing overall process complexity despite the added epitaxial step.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The epitaxial region growth process serves multiple functions simultaneously: it forms the source/drain regions, establishes electrical isolation, and restores/maintains compressive strain. This multi-functionality reduces the need for separate dedicated steps for each function, offsetting the added complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively maintains uniaxial strain between transistors, enhancing device performance by avoiding the degradation caused by fin cutting, while also reducing leakage through the use of dummy gates with a slightly longer channel length.

Implementation Method 1

growing a p-type doped epitaxial region at each of a plurality of source/drain regions between predetermined gate electrodes of the p-type field-effect transistors

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS9373624B1FinFET devices including epitaxially grown device isolation regions, and a method of manufacturing same
Publication Date: 2016.06.21 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9373624B1 patent drawing
  • US9373624B1 patent drawing
  • US9373624B1 patent drawing

AI summary

A method for manufacturing a semiconductor device including a plurality of fin field-effect transistor (FinFET) devices, comprises forming a plurality of fins on a substrate, wherein a first portion of the fins corresponds to p-type field-effect transistors, and a second portion of the fins corresponds to n-type field-effect transistors, forming a plurality of gate electrodes on the plurality of the fins, growing a p-type doped epitaxial region at each of a plurality of source/drain regions between predetermined gate electrodes of the p-type field-effect transistors, and growing an n-type doped epitaxial region at one or more areas between gate electrodes of respective adjacent p-type field-effect transistors to create one or more p-n junctions electrically isolating the adjacent p-type field-effect transistors from each other.