FinFET Epitaxial Source/Drain Profile Control

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Solution Overview

Problem

As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges such as increased gate-to-source/drain capacitance in FinFETs, which affects performance and efficiency.

Innovation Solution

The formation of epitaxial source/drain regions with varying flow-rate ratios of semiconductor material precursors during epitaxial growth processes, adjusting the gas-phase chlorine atoms introduction to achieve a taller and slimmer profile, thereby reducing gate-to-source/drain capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but gate-to-source/drain capacitance increases adversely affecting performance

Engineering Contradiction:
Improveintegration densityVSAvoidgate-to-source/drain capacitance
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies local quality by creating epitaxial source/drain regions with varying doping concentrations at different locations. The regions adjacent to the channel have lower doping concentrations, while regions farther away have higher doping concentrations, optimizing the electrical characteristics locally to reduce capacitance while maintaining overall device functionality

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the doping concentration parameter through multi-stage epitaxial growth processes. By controlling the flow rates of dopant precursors at different growth stages, the patent creates a gradient doping profile that reduces gate-to-source/drain capacitance while maintaining the scaled dimensions required for high integration density

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If epitaxial growth is performed with constant precursor flow rates, then the process is simple to control, but the resulting source/drain regions have suboptimal shape and adhesion

Engineering Contradiction:
Improveprocess control simplicityVSAvoidsource/drain region shape and adhesion
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies dynamics by transitioning from static, constant flow rate epitaxial growth to dynamic, time-varying flow rate profiles. The precursor flow rates are modulated during different stages of epitaxial growth to achieve optimal source/drain region shape and adhesion properties, with higher dopant flow rates initially and lower flow rates later in the growth process

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies preliminary action by performing a first epitaxial growth stage with specific dopant concentrations before performing a second growth stage with different dopant concentrations. This preliminary doping establishes a foundation that improves subsequent growth quality and adhesion, preparing the structure for optimal final properties

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a decreased gate-to-source/drain capacitance, enhancing the performance of FinFETs by optimizing the shape and adhesion of epitaxial source/drain regions, which is particularly beneficial for applications like ring oscillators.

Implementation Method 1

forming an epitaxial source/drain region in the recess, the forming including: growing a first layer lining sides and a bottom of the recess; and after growing the first layer, growing a second layer on the first layer

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

growing a first layer lining sides and a bottom of the recess by dispensing silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS10991630B2Semiconductor device and method
Publication Date: 2021.04.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10991630B2 patent drawing
  • US10991630B2 patent drawing
  • US10991630B2 patent drawing

AI summary

In an embodiment, a method includes: forming a first gate stack and a second gate stack on a fin; etching the fin to form a recess in the fin between the first gate stack and the second gate stack; forming an epitaxial source/drain region in the recess, the forming including: forming a first layer lining sides and a bottom of the recess by dispensing silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess; and after forming the first layer, forming a second layer on the first layer by dispensing the silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess, where each of the silane, dichlorosilane, trichlorosilane, and hydrochloric acid are dispensed at a first flow rate when forming the first layer and at a second flow rate when forming the second layer.