FinFET Epitaxial Source-Drain Segmentation for Uniformity
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving optimal integration density and minimizing degradation in FinFET devices due to issues with ion current variability and drain-induced barrier lowering, which affect device uniformity and wafer acceptance.
Innovation Solution
The formation of epitaxial source/drain regions with specific structural features, including void regions and epitaxial growth processes, is used to stabilize the epitaxial profile and improve device performance by encapsulating these regions within a dielectric layer, thereby enhancing isolation and contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain structures are used in FinFET devices, then manufacturing process is simpler, but ion current variability and drain-induced barrier lowering increase, degrading device uniformity
Solution Approach 1:
The source/drain region is segmented into multiple epitaxial layers with different compositions and properties. The structure includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, each with specific doping concentrations and material compositions that address different aspects of device performance, thereby reducing ion current variability and improving uniformity
Solution Approach 2:
The patent employs composite epitaxial structures combining different semiconductor materials (e.g., SiGe, SiC, Si) with varying germanium and carbon concentrations. These composite materials provide both stress control and electrical property optimization, reducing drain-induced barrier lowering while maintaining manufacturability through established epitaxial processes
2Productivity
If integration density is increased by reducing minimum feature size, then more components can be integrated into a given area, but device uniformity and wafer acceptance decrease due to ion current variability
Solution Approach 1:
The epitaxial structure implements local quality variations through spatially dependent doping concentrations and material compositions. The first, second, and third epitaxial layers have different doping profiles and material properties tailored to specific regions, which stabilizes ion current across the wafer and improves uniformity even as feature sizes are reduced for higher integration density
Solution Approach 2:
The patent systematically changes multiple parameters including germanium concentration, carbon concentration, doping density, and layer thickness across different epitaxial layers. These parameter variations are optimized to maintain device uniformity and wafer acceptance while enabling continued scaling for higher integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes Ion-Ioff degradation and drain-induced barrier lowering, leading to improved device uniformity and better wafer acceptance test results by optimizing the epitaxial profile and contact formation in FinFET devices.
Implementation Method 1
forming a plurality of epitaxial regrowth regions over respective ones of the plurality of fin structures
Data Source
AI summary
A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.