FinFET Epitaxial Layer Shape Control for Channel Management
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Solution Overview
Problem
Conventional FinFET fabrication processes result in fin structures being lower than surrounding shallow trench isolation due to over-etching, affecting the formation of epitaxial layers, which hampers control over the channel region and current between the source and drain.
Innovation Solution
The semiconductor device incorporates epitaxial layers with different shapes within different conductivity type regions, or within the same conductivity type region, using selective epitaxial growth methods to form crown, sub-epitaxial, and teeth epitaxial layers, ensuring a flat bottom surface for the recesses and adjusting the shape and thickness based on specific regions to improve flexibility and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional FinFET fabrication process is used to form recesses after removing part of fin structures, then epitaxial layer growth space is provided, but fin structures become lower than surrounding shallow trench isolation due to over-etching, affecting epitaxial layer formation
Solution Approach 1:
The patent performs preliminary etching to form recesses with flat bottom surfaces before epitaxial layer deposition. By pre-defining the recess geometry and depth, the subsequent epitaxial growth can proceed without interference from height variations, ensuring uniform layer formation while providing adequate growth space.
Solution Approach 2:
The patent creates locally differentiated structures by forming recesses only in specific regions where epitaxial layers are to be grown. The recesses have flat bottom surfaces that provide uniform nucleation sites for epitaxial growth, while the surrounding areas maintain their original fin structure geometry, thus achieving both growth space and height control.
2Ease of manufacture
If fin structures are lowered to accommodate epitaxial layer growth, then epitaxial layers can be formed, but control over channel region and current between source and drain is reduced
Solution Approach 1:
The patent establishes the recess geometry with flat bottom surfaces before epitaxial layer deposition. This preliminary structuring ensures that when epitaxial layers are grown, they do so from a controlled baseline, maintaining consistent channel lengths and effective gate control over the channel region while still accommodating the necessary layer thickness.
Solution Approach 2:
The patent controls the depth and geometry of recesses as key parameters, ensuring that the flat bottom surfaces are positioned at optimal depths that allow sufficient epitaxial layer growth while maintaining the channel region within the effective control range of the gate structures. This parameter optimization balances ease of manufacture with device reliability.
3Adaptability or versatility
If different shaped epitaxial layers are used in different conductivity type regions, then flexibility and control over channel region is improved, but device complexity increases
Solution Approach 1:
The patent implements different epitaxial layer shapes in different conductivity type regions (first and second conductivity type regions) to optimize performance for each transistor type. The first crown epitaxial layers and second epitaxial layers have different geometries tailored to their respective regions, providing local optimization while maintaining overall device functionality.
Solution Approach 2:
The patent divides the semiconductor device into distinct regions with different epitaxial layer configurations. By segmenting the device into first conductivity type region and second conductivity type region with各自 optimized epitaxial structures, the patent achieves adaptability for different applications while managing complexity through systematic regional differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the flexibility and control over the channel region, reducing drain-induced barrier lowering and short channel effects, while maintaining effective current between the source and drain by optimizing the epitaxial layer formation and shape within the FinFET structure.
Implementation Method 1
selective epitaxial growth methods to form crown, sub-epitaxial, and teeth epitaxial layers
Data Source
AI summary
The present invention provides a semiconductor structure, including a substrate having a first conductivity region and a second conductivity region defined thereon, a plurality of first fin structures and at least one first gate structure disposed on the substrate and within the first conductivity region, a plurality of second fin structures and at least one second gate structure disposed on the substrate and within the second conductivity region, at least two first crown epitaxial layers disposed within the first conductivity region, a plurality of second epitaxial layers disposed within the second conductivity region, where the shape of the first crown epitaxial layer is different from that of the second epitaxial layer.