Epitaxial Growth on FinFET Source/Drain Regions
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Solution Overview
Problem
In FinFET manufacturing, existing methods for epitaxial growth of semiconductor material on fins often result in reduced nucleation sites and integration challenges due to extensive insulator etching, leading to increased resistance and production yield issues, particularly in creating effective source/drain regions.
Innovation Solution
A method involving a partial etch to retain insulating material on fin sidewalls, followed by a recess to enhance nucleation sites and prevent lateral growth, allowing for epitaxial growth of semiconductor material only where necessary, and replacing original fin material with highly conductive semiconductor material to improve junctions and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If extensive insulator etching is performed to prepare the fin surface for epitaxial growth, then the fin surface is exposed for material deposition, but nucleation sites are reduced and integration challenges increase
Solution Approach 1:
The patent applies partial etching of the insulator layer rather than complete removal. The insulator is etched only in the source/drain regions to expose the fin surface where epitaxial growth is needed, while retaining the insulator in other areas. This selective partial action provides sufficient exposure for high-quality epitaxial growth without the excessive etching that would create integration challenges and reduce production yield.
Solution Approach 2:
The patent implements local quality by differentiating the treatment of the insulator layer across different regions. The source/drain regions receive etching treatment to expose fins for epitaxial growth, while other regions maintain the original insulator coverage. This localized approach ensures high manufacturing precision where needed without compromising overall device reliability.
2Manufacturing precision
If epitaxial growth is performed without retaining insulating material on fin sidewalls, then material can be deposited on exposed surfaces, but lateral growth occurs and junction sharpness decreases
Solution Approach 1:
The patent uses the insulator layer as an intermediary element that controls the epitaxial growth process. By retaining the insulator on fin sidewalls during growth, it acts as a physical barrier that prevents lateral material deposition. This intermediary structure enables precise vertical growth while blocking unwanted lateral expansion, thereby maintaining sharp junction profiles and reducing parasitic capacitance.
Solution Approach 2:
The patent applies preliminary anti-action by pre-positioning the insulator material on fin sidewalls before epitaxial growth begins. This pre-established barrier prevents the harmful lateral growth effect before it can occur, ensuring that the semiconductor material grows only in the desired vertical direction and maintains sharp, well-defined junctions.
3Reliability
If original fin material is replaced with highly conductive semiconductor material, then source/drain conductivity improves, but process complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the material composition parameter in the source/drain regions. The original fin material is replaced with highly conductive semiconductor material through epitaxial growth, changing the electrical conductivity parameter from moderate to high. This material substitution directly improves device performance while the selective nature of the process keeps complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the production yield and device performance by reducing unwanted capacitance and resistance, enabling embedded source/drain regions with improved conductivity and sharp junction profiles, similar to planar FETs but with FinFET dimensions.
Implementation Method 1
epitaxial growth of a semiconductor material on the exposed fin surface may be performed
Implementation Method 2
A surface refresh may be performed, where the surface refresh creates additional sites for epitaxial nucleation
Data Source
AI summary
A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.