FinFET Epitaxial Source/Drain Void Formation for Parasitic Capacitance Reduction
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Solution Overview
Problem
In the semiconductor industry, particularly in nanometer technology process nodes, the development of three-dimensional designs like Fin FETs faces challenges in reducing parasitic capacitance at the source/drain structure due to the complexity of epitaxial source/drain formation with voids, which affects device performance and efficiency.
Innovation Solution
The manufacturing process involves forming fin structures over a substrate, embedding them in an isolation insulating layer, and then creating a gate structure. The epitaxial source/drain structures are grown laterally, merging to form voids with the fin mask layer on the isolation insulating layer, which reduces parasitic capacitance by optimizing the fin mask layer's presence and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial source/drain structures are formed with voids to reduce parasitic capacitance, then device performance is improved, but the manufacturing process complexity increases
Solution Approach 1:
The fin mask layer is formed on the isolation insulating layer before epitaxial growth, pre-positioning the structure that will define the void formation. This preliminary action simplifies the overall process by establishing the void-defining framework before the complex epitaxial growth occurs, rather than requiring post-growth modifications.
Solution Approach 2:
The fin mask layer acts as an intermediary structure between the isolation insulating layer and the epitaxial source/drain structures. It mediates the formation of voids by being selectively removed in specific regions, enabling controlled void formation without directly complexifying the epitaxial growth process itself.
2Object-affected harmful factors
If the fin mask layer is retained on the isolation insulating layer to form voids, then parasitic capacitance is reduced, but the etching process complexity increases
Solution Approach 1:
The fin mask layer is selectively removed only in specific local regions where voids are desired, while being retained in other regions. This local quality approach allows precise control over void formation, reducing parasitic capacitance only where needed without requiring complex global etching patterns.
Solution Approach 2:
The etching process is segmented into selective removal steps that target specific portions of the fin mask layer. By dividing the mask layer removal into discrete, location-specific operations, the process achieves precise void formation while maintaining simplicity in each individual etching step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance at the source/drain structure, enhancing device performance and efficiency by allowing for better control over the epitaxial growth and void formation, thereby improving the overall semiconductor device's operational characteristics.
Implementation Method 1
The epitaxial source/drain structures are grown laterally, merging to form voids with the fin mask layer on the isolation insulating layer
Data Source
AI summary
A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.