FinFET Epitaxial Source-Drain Wrap-Around Contacts
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Solution Overview
Problem
The increasing device density in Fin FET devices leads to challenges in forming effective contact areas, resulting in limited contact area and increased parasitic resistance due to merged source/drain regions, which affects the performance and reliability of semiconductor transistors.
Innovation Solution
The formation of non-faceted, high aspect ratio epitaxial source/drain regions with wrap-around contacts that do not merge with adjacent fin devices, allowing for increased contact area and reduced parasitic resistance, while being compatible with existing FinFET-based CMOS device fabrication processes at low additional cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device density is increased in Fin FET devices, then higher device density is achieved, but contact area is reduced and parasitic resistance increases
Solution Approach 1:
The patent applies wrap-around contacts that extend laterally around the source/drain regions, transitioning from traditional top-only contacts to multi-dimensional contacts that access both upper and side surfaces. This dimensional expansion increases contact area without increasing device footprint, resolving the contradiction between high device density and sufficient contact area.
Solution Approach 2:
The source/drain regions are segmented into distinct epitaxial structures with different compositions (e.g., SiGe source, Si drain) that are laterally separated. This segmentation prevents merging of source/drain regions between adjacent fins, maintaining adequate contact area even at high device densities.
2Productivity
If device density is increased in Fin FET devices, then higher device density is achieved, but parasitic resistance increases
Solution Approach 1:
Wrap-around contacts provide additional lateral contact paths around the source/drain regions, creating parallel conduction paths that reduce parasitic resistance. The contacts extend onto side surfaces, effectively adding dimensional pathways for current flow that mitigate the harmful effect of parasitic resistance in high-density devices.
Solution Approach 2:
The wrap-around contact structure merges the top contact and side contact into a unified continuous conductive path that wraps around the source/drain region. This combined structure provides multiple simultaneous contact points, reducing overall parasitic resistance through parallel conduction pathways.
3Ease of manufacture
If conventional source/drain formation is used, then fabrication is simpler, but source/drain regions merge and contact area is limited
Solution Approach 1:
The patent employs selective epitaxial growth with controlled parameters (temperature, pressure, gas flow, composition) to form source/drain regions with specific properties. By adjusting epitaxial parameters, the source and drain regions grow with different compositions and rates, preventing merging while enabling wrap-around contact formation. This parameter control achieves both adequate contact area and manufacturing feasibility.
Solution Approach 2:
The methodology performs preliminary patterning and epitaxial growth steps that pre-establish the source/drain region geometry before final contact formation. Wrap-around contact openings are defined early in the process, allowing subsequent epitaxial growth to conformally fill the contact regions. This preliminary structuring ensures adequate contact area is achieved without requiring complex later modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the contact area and reduces parasitic resistance in Fin FET devices, preventing source/drain defects and improving device performance by allowing contact with both upper and side surfaces of the source/drain regions, thus enhancing the overall reliability and efficiency of the semiconductor transistors.
Implementation Method 1
conformal epitaxial source/drain regions
Data Source
AI summary
A semiconductor device includes a substrate, a fin structure disposed over the substrate and including a channel region and a source/drain region, a gate structure disposed over at least a portion of the fin structure, the channel region being beneath the gate structure and the source/drain region being outside of the gate structure, a strain material layer disposed over the source/drain region, the strain material layer providing stress to the first channel region, and a contact layer wrapping around the first strain material layer. A width of the source/drain region is smaller than a width of the channel region.