FinFET Source/Drain Epitaxy With As Barrier for P Diffusion Control
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Solution Overview
Problem
In Fin FET devices, phosphorus (P) diffusion from the SiP source/drain epitaxial layer into the channel region is not adequately suppressed, leading to performance issues, and existing methods are insufficient to prevent P out-diffusion effectively.
Innovation Solution
An arsenic (As) containing layer is used as a P diffusion barrier, either grown as a first epitaxial layer or implanted, and additional As containing layers are formed to prevent P out-gassing during contact metallization, with specific epitaxial layers and implantation processes to control the concentration and distribution of As and P.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher P concentration is used in SiP source/drain epitaxial layer, then resistivity is reduced and device performance is improved, but P diffusion into channel region increases and reliability deteriorates
Solution Approach 1:
An arsenic-containing barrier layer is introduced as an intermediary between the SiP source/drain epitaxial layer and the channel region. This barrier layer acts as a mediator that prevents phosphorus diffusion into the channel while allowing the high P concentration in SiP to maintain low resistivity. The barrier layer is formed by implanting As ions or depositing an As-containing layer before forming the SiP epitaxial layer.
Solution Approach 2:
The arsenic-containing barrier layer is formed in advance before the SiP source/drain epitaxial layer is deposited. This preliminary action establishes the diffusion barrier beforehand, preventing P diffusion during subsequent processing steps such as annealing or metallization. The barrier layer is prepared as part of the source/drain region formation process before final contact metallization is applied.
2Object-affected harmful factors
If conventional diffusion barrier methods are used, then P diffusion is partially suppressed, but the barrier is insufficient to prevent P out-diffusion during contact metallization
Solution Approach 1:
The invention changes the material parameter of the diffusion barrier from conventional materials to an arsenic-containing layer with specific properties. The As-containing layer has a different atomic mass and bonding characteristics that provide superior P diffusion blocking capability. The barrier layer may have specific thickness (e.g., 1-10 nm) and As concentration parameters that are optimized to prevent both P diffusion into the channel and P out-diffusion during metallization.
Solution Approach 2:
The source/drain region is structured as a composite material system consisting of multiple layers: the SiP epitaxial layer, the As-containing barrier layer, and contact metallization layers. This composite structure combines materials with complementary properties - SiP provides low resistivity, As-layer provides diffusion blocking, and metallization provides electrical contact. The composite structure enables simultaneous achievement of low resistivity and effective P diffusion prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The As containing layers effectively prevent P diffusion into the channel region, allowing for higher P concentration in the SiP body to reduce resistivity and prevent P out-gassing during metallization, thereby enhancing the reliability and performance of Fin FET devices.
Implementation Method 1
An As containing layer is formed over a source/drain region of a semiconductor layer to prevent diffusion of P into a channel region
Implementation Method 2
a first epitaxial layer is formed over the source/drain region, a second epitaxial layer is formed over the first epitaxial layer, and a third epitaxial layer is formed over the second epitaxial layer
Data Source
AI summary
A semiconductor device, includes a channel region, and a source/drain region adjacent to the channel region. The source/drain region includes a first epitaxial layer, a second epitaxial layer epitaxially formed on the first epitaxial layer and a third epitaxial layer epitaxially formed on the second epitaxial layer, and the first epitaxial layer is made of SiAs.