FinFET Epitaxy Below STI for Short-Channel and Fin-Bending Control

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Solution Overview

Problem

In the formation of Fin Field-Effect Transistors (FinFETs), the existing methods face challenges in controlling the epitaxy regions to prevent merging and ensure proper extension below Shallow Trench Isolation (STI) regions, leading to issues like short channel effects and fin bending.

Innovation Solution

The method involves forming semiconductor fins with recesses extending below the top surfaces of STI regions, followed by growing epitaxy regions that extend to these recesses, using a multi-layer epitaxy process with controlled doping concentrations and stressor layers to optimize the source/drain regions, and forming p-type FinFETs with cone-shaped epitaxy regions to mitigate fin bending.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If epitaxy regions are grown from recesses of neighboring semiconductor fins, then source/drain regions are formed, but the epitaxy regions may merge with each other causing planar top surfaces and potential short channel effects

Engineering Contradiction:
Improvecontrol of epitaxy region extensionVSAvoidshort channel effect
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a shielding layer pattern before epitaxy growth. This shielding layer is deposited and patterned to extend beyond the STI regions, creating a pre-configured structure that guides and confines the subsequent epitaxy region growth. The shielding layer prevents unwanted merging of epitaxy regions from neighboring fins while ensuring proper extension below STI regions, thereby resolving the contradiction between manufacturing precision and device reliability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If epitaxy regions extend below STI regions, then short channel effect is reduced, but control over epitaxy region profile and merging becomes difficult

Engineering Contradiction:
Improveshort channel effectVSAvoidepitaxy region profile control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent implements feedback control through the shielding layer mechanism. The shielding layer is strategically positioned and dimensioned to provide real-time confinement during epitaxy growth. As epitaxy regions grow from recesses of neighboring fins, the shielding layer acts as a physical barrier that prevents merging while allowing extension below STI regions. This feedback mechanism ensures that the epitaxy regions maintain the desired profile and extension depth, resolving the contradiction between reliability improvement and manufacturing precision.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If multi-layer epitaxy process with doping is used, then dopant control is enhanced, but process complexity increases

Engineering Contradiction:
Improvedopant controlVSAvoidepitaxy process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the epitaxy process into multiple distinct layers with different doping concentrations and materials. The multi-layer epitaxy structure includes separately formed layers, each with specific dopant profiles, allowing precise control over dopant distribution in the source/drain regions. This segmentation approach enhances manufacturing precision for dopant control while organizing the complexity into manageable, functionally distinct layers.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the short channel effect, enhances dopant control, and improves fin stability by extending epitaxy regions below STI levels, thereby enhancing the performance and reliability of FinFETs.

Implementation Method 1

growing epitaxy regions that extend to these recesses, using a multi-layer epitaxy process

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20240363636A1Epitaxy regions extending below STI regions and profiles thereof
Publication Date: 2024.10.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240363636A1 patent drawing
  • US20240363636A1 patent drawing
  • US20240363636A1 patent drawing

AI summary

A method includes forming isolation regions extending into a semiconductor substrate, forming a plurality of semiconductor fins protruding higher than top surfaces of the isolation regions, forming a gate stack on the plurality of semiconductor fins, forming a gate spacer on a sidewall of the gate stack, and recessing the plurality of semiconductor fins to form a plurality of recesses on a side of the gate stack. The plurality of recesses extend to a level lower than top surfaces of the isolation regions. Epitaxy processes are performed to grow an epitaxy region, wherein the epitaxy region fills the plurality of recesses.