FinFET Source/Drain Epitaxy With Lattice-Mismatched Cap Layer

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Solution Overview

Problem

Current FinFET manufacturing processes face challenges in achieving optimal stress induction and interfacial characteristics for source/drain structures, which affect current driving capacity and contact resistance.

Innovation Solution

Incorporating a base epitaxial layer with a cap epitaxial layer of differing lattice constants and surface roughness to induce appropriate stress and improve interfacial characteristics, with the cap epitaxial layer having a smoother surface than the base epitaxial layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single epitaxial layer is used for source/drain structures, then the manufacturing process is simple, but the stress induction and interfacial characteristics are insufficient

Engineering Contradiction:
Improveinterfacial characteristicsVSAvoidepitaxial layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The epitaxial layer is divided into two distinct segments: a base epitaxial layer and a cap epitaxial layer. The base layer provides the foundation with appropriate lattice constant for stress induction, while the cap layer with different lattice constant and smoother surface morphology enhances the interfacial characteristics and stress control, thereby resolving the contradiction between simplicity and performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a composite epitaxial structure where the base epitaxial layer and cap epitaxial layer are composed of different materials or have different compositions. This composite structure enables simultaneous achievement of stress induction through lattice constant differences and improved interfacial characteristics through the cap layer's smoother surface, overcoming the limitations of a single-material approach

Inventive Principle:
Principle #40Composite materials

2Productivity

If the surface of the epitaxial layer is rough, then the growth process is faster, but the contact resistance increases

Engineering Contradiction:
Improveepitaxial growth rateVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The epitaxial structure is segmented into a base layer that can be grown at higher rates with less stringent surface requirements, and a cap layer that is specifically optimized to provide a smooth surface finish. This segmentation allows the growth process to maintain productivity while the cap layer ensures low contact resistance through its smoother morphology

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cap epitaxial layer acts as an intermediary between the rougher base layer and the subsequent metal contact or gate structure. It provides a transition interface with improved surface quality, thereby reducing contact resistance without compromising the growth efficiency of the underlying base layer

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances current driving capacity and reduces contact resistance by applying compressive or tensile stress to the channel region, improving the overall performance of FinFETs.

Implementation Method 1

The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer... applying compressive or tensile stress to the channel region

Methodology Applied
Scientific EffectStress induction through lattice constant mismatch:

Data Source

PatentUS12021144B2Method of manufacturing a semiconductor device and a semiconductor device
Publication Date: 2024.06.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12021144B2 patent drawing
  • US12021144B2 patent drawing
  • US12021144B2 patent drawing

AI summary

A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.