FinFET Source/Drain Epitaxy for Uniform Contact Area

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Solution Overview

Problem

Current technologies for forming epitaxial source/drain features in semiconductor devices face challenges with critical dimension uniformity and device performance due to varying growth rates on different surface orientations and gate spacings, leading to non-uniform shapes and heights of epitaxial features, which affect contact resistance and transistor performance.

Innovation Solution

The formation of epitaxial source/drain features is controlled to have a higher growth rate on (100) surface orientations compared to (110) and (111) orientations, resulting in bar-like shapes in short channel regions and diamond-like shapes in long channel regions, increasing the raise height and surface area for better contact conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional epitaxial growth is used with standard gate spacing, then manufacturing process is simple, but critical dimension uniformity of source and drain contact deteriorates due to varying growth rates on different surface orientations

Engineering Contradiction:
Improvecritical dimension uniformityVSAvoidepitaxial growth process control
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by forming different epitaxial layer structures in different regions of the semiconductor device. Specifically, a first epitaxial layer structure is formed in a first region with a first thickness, while a second epitaxial layer structure is formed in a second region with a second thickness greater than the first thickness. This regional differentiation addresses the varying growth rates on different surface orientations and gate spacings, ensuring uniform critical dimensions across the entire device structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements parameter changes by selectively adjusting the thickness of epitaxial layers based on regional requirements. The method involves forming a first epitaxial layer with a first thickness in a first region and a second epitaxial layer with a second thickness in a second region, where the second thickness is greater than the first thickness. This parameter variation compensates for the effects of different surface orientations and gate spacings, achieving uniform critical dimensions across diverse device regions.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If epitaxial features are formed with uniform thickness across all regions, then fabrication process is simplified, but contact resistance increases due to insufficient surface area for source/drain contacts

Engineering Contradiction:
Improvecontact conductivityVSAvoidepitaxial layer formation
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies local quality by forming different epitaxial layer structures in different regions of the semiconductor device. Specifically, a first epitaxial layer structure is formed in a first region with a first thickness, while a second epitaxial layer structure is formed in a second region with a second thickness greater than the first thickness. This regional differentiation addresses the varying growth rates on different surface orientations and gate spacings, ensuring uniform critical dimensions across the entire device structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs dimensionality change by varying the thickness of epitaxial layers in the vertical dimension across different horizontal regions. By forming a thicker second epitaxial layer structure in the second region compared to the first epitaxial layer structure in the first region, the invention increases the surface area available for source/drain contacts in specific areas, thereby reducing contact resistance without complicating the overall fabrication process.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If gate spacing is reduced to increase device density, then device density improves, but epitaxial feature shape uniformity deteriorates due to different growth rates on (100), (110), and (111) surface orientations

Engineering Contradiction:
Improvedevice densityVSAvoidepitaxial feature shape uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by forming different epitaxial layer structures in different regions of the semiconductor device. Specifically, a first epitaxial layer structure is formed in a first region with a first thickness, while a second epitaxial layer structure is formed in a second region with a second thickness greater than the first thickness. This regional differentiation addresses the varying growth rates on different surface orientations and gate spacings, ensuring uniform critical dimensions across the entire device structure.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements parameter changes by selectively adjusting the thickness of epitaxial layers based on regional requirements. The method involves forming a first epitaxial layer with a first thickness in a first region and a second epitaxial layer with a second thickness in a second region, where the second thickness is greater than the first thickness. This parameter variation compensates for the effects of different surface orientations and gate spacings, achieving uniform critical dimensions across diverse device regions.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces contact resistance and enhances device performance by increasing the surface area for subsequent source/drain contacts, improving the performance of transistors in both short and long channel regions without compromising critical dimension uniformity.

Implementation Method 1

The formation of epitaxial source/drain features is controlled to have a higher growth rate on (100) surface orientations compared to (110) and (111) orientations

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20240186388A1Semiconductor device with improved source and drain contact area and methods of fabrication thereof
Publication Date: 2024.06.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240186388A1 patent drawing
  • US20240186388A1 patent drawing
  • US20240186388A1 patent drawing

AI summary

Semiconductor device includes a substrate having a plurality of fins formed from the substrate, a first source/drain feature comprising a first epitaxial layer in contact with a first fin of the plurality of fins, and a second epitaxial layer formed over the first epitaxial layer, the second epitaxial layer comprising a first facet and a second facet connecting to the first facet, a second source/drain feature disposed adjacent to the first source/drain feature, the second source/drain feature comprising a first epitaxial layer in contact with a second fin of the plurality of fins a second epitaxial layer formed over the first epitaxial layer of the second source/drain feature, the second epitaxial layer of the second source/drain feature comprising a third facet and a fourth facet connecting to the third facet, and a third epitaxial layer comprising a first center portion disposed above and in contact with the first facet and the second facet, and a second center portion disposed above and in contact with the third facet and the fourth facet.