FinFET Source/Drain Epitaxy for Non-Faceted Contact Surfaces

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Solution Overview

Problem

Challenges in implementing three-dimensional FinFET designs, such as FinFETs, arise from fabrication and design issues, particularly in achieving a non-faceted top surface for epitaxial source/drain regions, which affect contact resistance and device performance.

Innovation Solution

A process flow involving multiple deposition and etch back processes using silane (SiH4) and phosphine (PH3) precursors in high temperature and low pressure environments, controlled by SiH4 passivation and hydrochloric acid (HCl) etching, to form non-faceted epitaxial source/drain regions with increased contact landing area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional deposition processes are used to form epitaxial source/drain regions, then the regions are formed efficiently, but faceted top surfaces are created which increase contact resistance and reduce device performance

Engineering Contradiction:
Improvesurface morphologyVSAvoidcontact resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies parameter changes by modifying deposition conditions (temperature, pressure, gas flow rates) and etching parameters (etchant composition, temperature, time) to transform the surface morphology from faceted to non-faceted. Specifically, the multi-step process uses different temperature ranges (600-800°C for deposition, 700-900°C for etching) and pressure conditions to control crystal growth and remove facets, thereby reducing contact resistance while maintaining manufacturing efficiency

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts the harmful faceted surfaces through selective etching processes. The first etch back process specifically targets and removes the faceted top surfaces that formed during deposition, separating the unwanted facet structure from the desired epitaxial region. This extraction eliminates the source of high contact resistance while preserving the underlying beneficial epitaxial structure

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If the contact landing area is increased to reduce contact resistance, then device performance improves, but the fabrication process complexity increases

Engineering Contradiction:
Improvecontact resistanceVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the deposition and etching processes into multiple distinct steps with specific parameters for each stage. The deposition is divided into initial growth and final capping stages, while etching is segmented into first etch back (removing facets) and second etch back (final planarization). This segmentation allows each step to be optimized independently, managing overall process complexity while achieving the desired non-faceted surface with increased contact area

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by forming a sacrificial oxide layer before deposition and using it as a mask during etching. The oxide layer is formed in advance to define the contact region boundaries, and the preliminary deposition creates a buffer layer that protects underlying structures. These preliminary actions establish the framework for subsequent processing, enabling precise control of contact landing area without proportionally increasing overall process complexity

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The process enhances device performance by reducing contact resistance and increasing the contact landing area for FinFETs, suitable for applications in static random access memory (SRAM) devices.

Implementation Method 1

controlled by SiH4 passivation

Methodology Applied
Scientific EffectPassivation: Adsorption

Implementation Method 2

hydrochloric acid (HCl) etching

Methodology Applied
Scientific EffectChemical etching: Chemical Bonding

Implementation Method 3

epitaxially growing

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 4

deposition processes using silane (SiH4) and phosphine (PH3) precursors

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS12402344B2FETS and methods of forming FETS
Publication Date: 2025.08.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12402344B2 patent drawing
  • US12402344B2 patent drawing
  • US12402344B2 patent drawing

AI summary

An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.