FinFET Epitaxy Doping for Carrier Mobility and Contact Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher device density, performance, and lower costs, particularly in the fabrication and design of FinFET devices, where current methods struggle to optimize current flow and reduce short-channel effects effectively.
Innovation Solution
The method involves forming semiconductor fins on a substrate using photolithography and etching techniques, followed by the formation of gate structures and epitaxy features, and employing plasma doping and annealing processes to create doped source/drain portions that enhance carrier mobility and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional fabrication methods are used for FinFET devices, then manufacturing process simplicity is maintained, but device density and performance optimization are insufficient
Solution Approach 1:
The fabrication process is divided into multiple patterning steps (first and second photolithography processes, first and second etching processes) to create complex fin structures with different orientations and configurations, enabling higher device density while managing process complexity through systematic breakdown of the fabrication sequence
Solution Approach 2:
The patent transitions from planar transistor structures to three-dimensional FinFET structures with vertical fins extending from the substrate, utilizing the vertical dimension to increase effective channel area and device density without proportionally increasing the footprint area
2Reliability
If standard doping methods are used, then process simplicity is maintained, but carrier mobility and contact resistance optimization are insufficient
Solution Approach 1:
Dopant layers are deposited and patterned in advance before the final annealing step, with specific dopant regions formed in source/drain areas and channel regions at different stages of the fabrication process, allowing optimized doping profiles to be achieved before device operation
Solution Approach 2:
The patent employs multiple annealing processes at different temperatures and durations to control dopant diffusion and activation, changing thermal parameters to optimize carrier mobility and reduce contact resistance in different device regions
3Reliability
If uniform doping is applied throughout the fin structure, then manufacturing simplicity is maintained, but short-channel effects are not effectively reduced
Solution Approach 1:
Different dopant concentrations and types are applied to different regions of the fin structure, with heavily doped source/drain regions, lightly doped channel regions, and selectively doped areas to create optimal electrical characteristics for each functional zone while mitigating short-channel effects
Solution Approach 2:
The patent applies dopants in excess in certain regions (such as source/drain extensions) and uses selective removal or activation steps to achieve the desired non-uniform doping profile, allowing enhanced doping in critical areas while maintaining control over overall device characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and device performance by straining the channel portion of the semiconductor fins, reducing contact resistance, and allowing for higher impurity concentrations, thereby enhancing the overall performance and efficiency of FinFET devices.
Implementation Method 1
plasma doping and annealing processes
Implementation Method 2
plasma doping process
Implementation Method 3
diffusing a dopant from the dopant source layer into the epitaxy feature through the capped top surface and the sidewall of the epitaxy feature
Implementation Method 4
forming semiconductor fins on a substrate using photolithography and etching techniques
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a dielectric feature and an epitaxy feature. The epitaxy feature is on the semiconductor substrate. The epitaxy feature has a top central portion and a corner portion. The dielectric feature is closer to the corner portion than the top central portion, and the corner portion has an impurity concentration higher than that of the top central portion.