FinFET Source/Drain Epitaxy Layout to Prevent Structure Merging
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Solution Overview
Problem
Conventional fin field-effect transistors face challenges in preventing the merging of epitaxial structures of source/drain regions, which limits the density of transistors per unit area due to the need for large spaces between them, and increases power consumption due to increased leakage current.
Innovation Solution
A fin field-effect transistor design where the growth of source/drain regions is restricted in the Y-axis direction using a selective epitaxial growth process, with an insulating layer formed between the gate and source/drain regions to control the lateral growth, allowing for reduced size and adjusted dimensions of the epitaxial structures without additional etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth is performed to form source/drain regions, then impurity diffusion is reduced and mobility is improved, but the epitaxial structures grow into a diamond structure occupying larger area, requiring more space between transistors
Solution Approach 1:
The patent applies dimensionality change by performing selective etching to remove the diamond-shaped upper portions of the epitaxial structures, transforming them into columnar shapes. This dimensional modification reduces the lateral footprint of source/drain regions while preserving their vertical structure, thereby reducing the space required between transistors without compromising the mobility benefits of selective epitaxial growth
Solution Approach 2:
The patent extracts the problematic diamond-shaped upper portions of the epitaxial structures through selective etching processes. By removing these protruding sections that cause merging between adjacent transistors, the patent maintains the beneficial lower portions of the epitaxial structures while eliminating the space-consuming features
2Productivity
If device size is reduced to several tens of nanometers to increase transistor density, then unit area and power consumption are reduced, but leakage current through the channel increases
Solution Approach 1:
The patent applies parameter changes by modifying the physical dimensions and shape of source/drain regions through selective etching. By changing the epitaxial structure from diamond-shaped to columnar, the patent alters the geometric parameters to reduce leakage current while maintaining the scaled-down device dimensions needed for high transistor density
Solution Approach 2:
The patent introduces an intermediary approach by using selective etching as a mediating process between epitaxial growth and final device formation. This intermediary step allows optimization of source/drain region geometry to simultaneously achieve low leakage current and high transistor density
3Area of stationary object
If quartz etching process is performed to reduce epitaxial structure widths, then merging is prevented, but process complexity increases and additional costs are required
Solution Approach 1:
The patent merges the epitaxial growth process with the source/drain region formation process by performing selective etching immediately after epitaxial growth while the structures are still in the appropriate state. This combined approach eliminates the need for separate quartz etching processes, reducing overall process complexity while achieving the same size-reduction goal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents the merging of epitaxial structures, increases transistor density, reduces parasitic capacitance, and lowers power consumption by minimizing the size of source/drain regions while maintaining processing costs and reducing variability in device characteristics.
Implementation Method 1
a selective epitaxial growth (hereinafter, referred to as 'SEG') process, which is capable of being performed at relatively low temperatures when the source/drain regions are formed
Data Source
AI summary
Disclosed is a fin field-effect transistor having size-reduced source/drain regions so that a merging phenomenon of epitaxial structures between transistors in a layout is prevented, thus increasing the number of transistors per unit area, and so that an additional mask process is not required, thus maintain processing costs without change, and a method of manufacturing the same.