FinFET Source/Drain Epitaxy Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with improved power efficiency poses challenges due to the need for finer patterns and the limitations of planar metal oxide semiconductor field effect transistors (MOSFETs).
Innovation Solution
A semiconductor device design featuring active regions with a fin structure, intersecting gate structures, and source/drain regions with epitaxial layers of varying thickness and depth, optimized to improve power efficiency by managing channel layers and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar metal oxide semiconductor field effect transistors (MOSFETs) are used, then manufacturing is simpler, but power efficiency deteriorates and performance is limited
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET channel structures, adding vertical dimensionality to improve carrier control and reduce short-channel effects, thereby enhancing power efficiency while maintaining manufacturing feasibility through established semiconductor fabrication processes
2Productivity
If device size is reduced for high integration, then productivity increases, but operating characteristics deteriorate due to short-channel effects
Solution Approach 1:
The FinFET structure utilizes vertical fins extending from the substrate, creating a three-dimensional channel that maintains effective channel length control even as horizontal device dimensions are reduced, enabling high integration density without sacrificing operating characteristics
Solution Approach 2:
The patent implements multiple channel layers stacked vertically within each FinFET structure, creating a nested configuration where multiple channels are contained within a single device footprint, thereby achieving high integration density while maintaining reliable channel control through the gate structure
3Productivity
If channel layers are stacked vertically to improve integration, then productivity increases, but parasitic capacitance increases reducing power efficiency
Solution Approach 1:
The patent employs silicon germanium (SiGe) materials for the channel layers and employs carefully engineered dielectric materials for isolation, creating a composite structure that reduces parasitic capacitance between stacked channels while maintaining high integration density through the vertical channel stacking
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed semiconductor device achieves improved power efficiency by optimizing the structure of source/drain regions and channel layers, reducing parasitic capacitance and enhancing performance in high-integration devices.
Implementation Method 1
each of the first and second source/drain regions includes a first epitaxial layer on each of the active regions in each of the recess regions, and a second epitaxial layer on the first epitaxial layer
Data Source
AI summary
A semiconductor device includes active regions extending on a substrate in a first direction, gate structures intersecting the active regions and extending on the substrate in a second direction, source/drain regions in recess regions in which the active regions are recessed, on both sides of each of the gate structures, and contact plugs connected to the source/drain regions, wherein each of the source/drain regions include first and second epitaxial layers sequentially stacked on the active regions in the recess regions in a third direction perpendicular to an upper surface of the substrate, respectively, and wherein ratios of the first epitaxial layer thickness in the third direction to the second epitaxial layer thickness in the third direction are different in different ones of the source/drain regions.