FinFET Source/Drain Epitaxy with Phosphorus Cladding Control
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Solution Overview
Problem
The scaling down of semiconductor integrated circuit (IC) devices to achieve increased performance and reduced geometry has increased manufacturing complexity, requiring advanced IC fabrication techniques, particularly in forming multi-gate fin-type transistors (finFET devices) where precise control over gate width and doping concentrations is necessary to prevent unwanted merge issues and maintain device performance.
Innovation Solution
The fabrication process involves forming finFET devices with a gate structure including a gate dielectric layer and electrode, using a sacrificial gate process and metal gate structure, and epitaxially growing doped source/drain regions with controlled phosphorus concentrations to prevent lateral expansion and ensure uniformity, along with a capping layer and interlayer dielectric to support further processing and interconnect formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device feature size is decreased to achieve scaling down, then production efficiency and performance are improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate formation process into multiple distinct stages: forming sacrificial gates, depositing metal gate materials, and performing selective etching. This segmentation allows each step to be optimized independently, managing the increased manufacturing complexity while maintaining scaling benefits
Solution Approach 2:
The patent employs preliminary actions by forming sacrificial gates before the final metal gate deposition, and by pre-defining source/drain regions through epitaxial growth with specific doping concentrations. These preliminary structures guide subsequent processing steps, reducing overall manufacturing complexity despite device scaling
2Length of moving object
If gate width is reduced in finFET devices, then device geometry is improved, but control over gate width becomes more difficult
Solution Approach 1:
The patent uses sacrificial gates as intermediary structures that define the gate width during processing. These sacrificial gates serve as templates that are later replaced by the final metal gate, providing precise geometric control while allowing flexibility in the final gate material composition
Solution Approach 2:
The patent controls gate width by adjusting multiple parameters including the thickness and composition of sacrificial gate materials, the dimensions of etch selectivity layers, and the doping concentrations in epitaxial regions. These parameter changes enable precise gate width control at reduced dimensions
3Reliability
If doping concentration is increased in source/drain regions, then device performance is improved, but unwanted merge issues between adjacent regions occur
Solution Approach 1:
The patent applies local quality by creating spatial variations in doping concentration within source/drain regions. Epitaxial growth is performed with different phosphorus concentrations at different locations and depths, providing high doping where needed for performance while maintaining lower doping in regions where merge prevention is critical
Solution Approach 2:
The patent converts the potential harmful effect of high doping-induced merging into a benefit by using controlled epitaxial growth that promotes vertical expansion. The high phosphorus concentration is directed primarily in the vertical direction, transforming what could be a merging problem into a beneficial strain effect that improves carrier mobility without causing lateral merge issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of finFET devices with improved channel electron mobility, reduced channel resistance, and prevention of unwanted merge issues between adjacent source/drain regions, enhancing the performance and efficiency of IC devices.
Implementation Method 1
epitaxially growing doped source/drain regions with controlled phosphorus concentrations
Data Source
AI summary
A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate structure is formed extending across the semiconductor fin. Recesses are etched in the semiconductor fin. Source/drain epitaxial structures are formed in the recesses in the semiconductor fin. Formation of each of the source/drain epitaxial structures comprises performing a first epitaxy growth process to form a bar-shaped epitaxial structure in one of the recesses, and performing a second epitaxy growth process to form a cladding epitaxial layer cladding on the bar-shaped epitaxial structure. The bar-shaped epitaxial structure has a lower phosphorous concentration than the cladding epitaxial layer.