FinFET Source/Drain Epitaxy Using Plasma Oxidation Selectivity
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Solution Overview
Problem
As semiconductor devices become increasingly integrated, it is challenging to achieve desired transistor performance, particularly in fin field effect transistors, due to limitations in the growth of source/drain regions.
Innovation Solution
A method involving patterning a substrate, forming a gate pattern, and using a plasma oxidation process to create a growth-inhibiting layer that is thicker on the gate pattern than on the active pattern, allowing for selective epitaxial growth of source/drain electrodes by exposing the active pattern portions, thereby enabling precise control over the growth of silicon-germanium patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain region growth methods are used in highly integrated semiconductor devices, then manufacturing simplicity is maintained, but transistor performance deteriorates due to inability to achieve desired source/drain region characteristics
Solution Approach 1:
The patent applies local quality by forming a growth-inhibiting layer selectively on the gate pattern sidewalls using plasma oxidation. This creates different growth conditions in different locations: the growth-inhibiting layer prevents source/drain material growth on the gate sidewalls, while the exposed active pattern regions allow normal growth. This local differentiation enables precise control over source/drain region formation, achieving desired transistor performance without requiring overly complex manufacturing processes.
2Manufacturing precision
If source/drain regions are grown without selective control, then manufacturing process is simple, but manufacturing precision deteriorates due to inability to control growth location and characteristics
Solution Approach 1:
The patent employs preliminary action by forming the growth-inhibiting layer on the gate pattern sidewalls before the source/drain region growth step. This preliminary formation of the growth-inhibiting layer pre-establishes the boundaries and conditions for subsequent source/drain material deposition, ensuring precise control over where growth occurs. The gate spacer and growth-inhibiting layer are prepared in advance to define the exact regions where source/drain electrodes will form, achieving high manufacturing precision.
Solution Approach 2:
The growth-inhibiting layer serves as an intermediary element between the gate pattern and the source/drain material. It mediates the growth process by selectively blocking material deposition on gate sidewalls while allowing growth in active regions. This intermediary layer enables precise spatial control of source/drain region formation without requiring direct complex patterning of each source/drain region, thus improving manufacturing precision with manageable process complexity.
3Manufacturing precision
If growth-inhibiting layer is formed uniformly, then process simplicity is maintained, but manufacturing precision deteriorates due to inability to expose active pattern portions for selective growth
Solution Approach 1:
The patent implements local quality by creating a growth-inhibiting layer with non-uniform thickness and coverage. The growth-inhibiting layer is formed specifically on the gate pattern sidewalls through plasma oxidation, leaving the active pattern regions exposed. This local differentiation in layer formation achieves precise control over which areas will receive source/drain material, enabling selective growth with improved manufacturing precision while maintaining reasonable process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the selective growth of source/drain regions, enhancing transistor performance by providing compressive or tensile strain, which improves the overall efficiency and integration of semiconductor devices.
Implementation Method 1
The growth-inhibiting layer may be formed by a plasma oxidation process
Data Source
AI summary
The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.