FinFET Epitaxy Control via Segmented Trench Isolation
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in efficiently forming non-planar multiple-gate FinFETs with precise control over trench depths and epitaxy structures to enhance carrier mobility and integration density.
Innovation Solution
The method involves forming trenches and isolation structures in a semiconductor substrate, followed by the deposition and recessing of dielectric material, and the formation of a gate stack and epitaxy structures to create strained channel regions, allowing for increased integration density and improved device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing techniques are used to form FinFETs, then the manufacturing process is simpler, but the carrier mobility and integration density are insufficient
Solution Approach 1:
The substrate is divided into multiple trenches with different depths, creating segmented regions that allow independent control of epitaxy growth in different areas. This segmentation enables precise control over channel strain and carrier mobility while maintaining a systematic manufacturing approach
Solution Approach 2:
Different regions of the substrate are given different local properties through selective trench formation and epitaxy growth. Shallow trenches and deep trenches create localized strain conditions optimized for specific device performance requirements, allowing carrier mobility enhancement in targeted areas without affecting the entire wafer
2Manufacturing precision
If trench depths are not precisely controlled, then the manufacturing process is easier, but the epitaxy structure profiles and device performance are compromised
Solution Approach 1:
Trenches are formed with predetermined depth variations before epitaxy growth, establishing a prepared substrate structure that guides subsequent material deposition. This preliminary structuring ensures that epitaxy grows in controlled strain environments, achieving precise trench depth control as an enabling step rather than a final adjustment
Solution Approach 2:
The manufacturing process incorporates dynamic control of trench depths through selective etching and filling operations, allowing the substrate structure to be adaptively modified. This dynamic approach enables precise depth control while maintaining flexibility in the manufacturing sequence
3Productivity
If integration density is increased, then device size is reduced, but control over epitaxy structures becomes more difficult
Solution Approach 1:
The substrate is segmented into multiple isolation regions with trenches of varying depths, allowing independent epitaxy control in each segment. This segmentation enables high integration density through compact device spacing while maintaining precise epitaxy structure control through localized process parameters
Solution Approach 2:
Epitaxy growth parameters are changed locally across different substrate regions, with distinct temperature, pressure, or composition conditions applied to shallow versus deep trench areas. This parameter differentiation enables precise control over epitaxy structures even as integration density increases and device features become more closely spaced
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor devices with enhanced carrier mobility and increased integration density, improving transistor performance and reducing size, while maintaining control over trench depths and epitaxy structure profiles.
Implementation Method 1
a plurality of epitaxy structures are formed on the semiconductor fins
Data Source
AI summary
A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structures, and a plurality of epitaxy structures. The substrate has a plurality of semiconductor fins therein. The first isolation structure is disposed between the semiconductor fins. The semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure. The epitaxy structures are respectively disposed on the semiconductor fins. The epitaxy structures are separated from each other, and at least one of the epitaxy structures has a substantially round profile.