FinFET Source-Drain Epitaxy with Sacrificial Sidewall Isolation
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Solution Overview
Problem
The challenge in manufacturing fin field effect transistors is the risk of forming a bridge between the source-drain epitaxial layer and the gate, which degrades device performance due to increased volume of the embedded epitaxial layer, especially at technology nodes below 20 nm.
Innovation Solution
The method involves forming a sacrificial sidewall to fill the bridge path before filling the epitaxial layer, preventing the formation of a bridge between the source-drain epitaxial layer and the gate by ensuring the epitaxial layer does not grow into the bridge path during the filling process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the volume of the embedded epitaxial layer is increased to improve stress function and carrier mobility, then device performance is improved, but the risk of generating a bridge between the gate and source-drain epitaxial layer increases
Solution Approach 1:
The method performs preliminary actions by forming the gate structure first, then creating the source and drain regions with embedded epitaxial layers. By establishing the gate structure before introducing the epitaxial layers, the process ensures that even as epitaxial layer volume increases for stress optimization, the gate structure is already in place to prevent bridge formation, thus resolving the contradiction between improving device performance and preventing harmful bridge formation.
2Ease of operation
If the embedded epitaxial layer volume is increased to enhance stress in the channel area, then carrier mobility is improved, but the structural integrity between gate and source-drain regions is compromised
Solution Approach 1:
The gate structure is formed in advance before the source and drain regions are created. This preliminary formation of the gate structure establishes a stable reference point that prevents structural integrity issues even when the embedded epitaxial layer volume is increased to enhance carrier mobility through stress effects.
Solution Approach 2:
The transistor structure is segmented into distinct regions: the gate structure, the fin region with embedded epitaxial layers, and the isolation regions. This segmentation allows the embedded epitaxial layers to be optimized for stress and carrier mobility while the gate structure maintains structural integrity, as each region can be independently optimized without compromising the whole.
Data Source
AI summary
The present application discloses a method for manufacturing a fin field effect transistor, comprising: step 1: forming fins; step 2, forming first gate structures; and step 3, forming source and drain areas, comprising: step 31: forming a second hard mask layer; step 32: opening a formation area of FinFET, and performing the first time etching on the second hard mask layer; step 33: performing the second time etching to form first grooves in the fins, wherein the second time etching vertically and horizontally etches the isolation dielectric layer, when the second groove is formed next to the exposed surfaces of the isolation dielectric layer, the exposed surfaces of the fins and the first polysilicon gate, as the result, the second groove forms a bridge path; step 34: forming a sacrificial sidewall to fully fill the bridge path; and step 35: filling the first groove with an epitaxial layer.