FinFET Epitaxy Profile Control for Clear SiGe Interfaces
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Solution Overview
Problem
In the formation of integrated circuits, there is a challenge in achieving clear interfaces and minimizing transition regions between silicon or silicon germanium regions, while also controlling the height of semiconductor fins to reduce waste and performance degradation.
Innovation Solution
The process involves etching trenches in a semiconductor substrate, growing epitaxy regions within these trenches, and controlling the profiles of these regions to prevent encroachment of silicon or silicon germanium into incorrect fins, using techniques such as pre-clean processes and epitaxial growth to achieve precise corner rounding and co-planarity across different device regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If epitaxy regions are grown to fill trenches completely, then the fin height is increased, but the interface clarity between silicon and silicon germanium regions deteriorates due to excessive encroachment
Solution Approach 1:
A pre-clean process is performed on the silicon layer before epitaxial growth to remove contaminants and prepare the surface. This preliminary action ensures that the subsequent epitaxy growth produces regions with controlled encroachment and clear interfaces, resolving the contradiction between achieving sufficient fin height and maintaining interface clarity
Solution Approach 2:
The epitaxial growth process parameters are optimized to control the encroachment of silicon germanium into silicon fins. By adjusting growth conditions, the patent achieves complete trench filling for adequate fin height while limiting excessive encroachment to maintain clear material interfaces and device performance
2Manufacturing precision
If the encroachment of silicon germanium into silicon fins is reduced, then the interface clarity is improved, but the fin height control becomes more difficult
Solution Approach 1:
The pre-clean process is applied before epitaxial growth to prepare the silicon layer surface. This preliminary action enables subsequent controlled epitaxy that achieves both clear interfaces and proper fin height by ensuring uniform nucleation and growth conditions across the substrate
Solution Approach 2:
Epitaxial growth parameters are specifically tuned to achieve the right balance between limiting silicon germanium encroachment and ensuring complete trench filling. The growth conditions are optimized so that interfaces remain clear while fins achieve sufficient height for device operation
3Manufacturing precision
If the top surfaces of epitaxy regions in different device regions are at the same level, then the co-planarity is improved, but the polishing rate differences between regions cause performance variation
Solution Approach 1:
The patent intentionally creates asymmetric loading by forming epitaxy regions at different levels in different device regions. Input/output regions have different epitaxy thickness than logic regions, which compensates for differences in polishing rates during CMP processing, ensuring uniform final co-planarity and consistent device performance across the wafer
Solution Approach 2:
Different epitaxial loading is applied to different device regions based on their specific requirements. Input/output device regions receive different epitaxy thickness compared to logic device regions, creating local variations that compensate for regional polishing rate differences and achieve uniform performance across the entire wafer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of Fin Field-Effect Transistors (FinFETs) with improved co-planarity and reduced encroachment, leading to more uniform performance and reduced waste, thereby enhancing the efficiency and performance of integrated circuits.
Implementation Method 1
performing an epitaxy process to form a first silicon germanium region and a second silicon germanium region in the first trench and the second trench, respectively
Implementation Method 2
performing a pre-clean process on the silicon layer
Implementation Method 3
performing a baking process on the wafer
Data Source
AI summary
A method includes etching a silicon layer in a wafer to form a first trench in a first device region and a second trench in a second device region, performing a pre-clean process on the silicon layer, performing a baking process on the wafer, and performing an epitaxy process to form a first silicon germanium region and a second silicon germanium region in the first trench and the second trench, respectively. The first silicon germanium region and the second silicon germanium region have a loading in a range between about 5 nm and about 30 nm.