FinFET Epitaxy Source/Drain Formation via Selective Growth Cycles
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Solution Overview
Problem
The scaling down of Integrated Circuit (IC) technology has increased complexity in processing and manufacturing, particularly in the formation of Fin Field-Effect Transistors (FinFETs), where existing methods struggle to effectively form epitaxy source/drain regions with precise control and high efficiency.
Innovation Solution
The method involves forming semiconductor fins, patterning hard masks, performing anisotropic and isotropic etches to create trenches, forming isolation regions, depositing and etching back epitaxy materials to form source/drain regions, and using multiple deposition-etch-back cycles to achieve precise control and high impurity concentrations in epitaxy regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing methods are used to form epitaxy source/drain regions in FinFETs, then the basic structure can be formed, but precise control and high efficiency are not achieved
Solution Approach 1:
The patent divides the epitaxy source/drain region formation into multiple discrete steps: forming seed regions, selective epitaxial growth, etching back, and repeated cycles. This segmentation allows precise control over each stage while maintaining overall manufacturing efficiency through systematic process organization.
Solution Approach 2:
The patent performs preliminary actions by forming seed regions and isolation structures before the main epitaxial growth. These preparatory steps establish controlled nucleation sites and prevent unwanted bridging, enabling subsequent precise epitaxy formation without requiring complex real-time adjustments.
2Productivity
If scaling down is performed to increase functional density, then production efficiency increases and costs decrease, but processing complexity increases
Solution Approach 1:
The patent employs universal process steps that can be applied across different FinFET generations and scaling nodes. The repeated cycles of epitaxial growth, etching, and deposition serve multiple functions: controlling dimensions, forming doping regions, creating stress patterns, and preventing bridging, thereby managing complexity through standardized multi-functional operations.
Solution Approach 2:
The patent implements nested process cycles where each cycle contains embedded steps (deposition, etching, annealing) that are repeated and nested within the overall FinFET fabrication sequence. This nesting allows systematic scaling while maintaining process control through hierarchical process organization.
3Manufacturing precision
If multiple deposition-etch-back cycles are performed to achieve precise control, then manufacturing precision improves, but processing time increases
Solution Approach 1:
The patent maintains continuity by performing repeated epitaxial growth and etching cycles without breaking the process flow. Each cycle builds upon the previous one, continuously refining the source/drain region geometry and composition. This continuous action achieves high precision while minimizing idle time between critical process steps.
Solution Approach 2:
The patent employs periodic repetition of deposition-etch-back cycles with controlled parameters. Each periodic cycle contributes incrementally to the final precision, allowing systematic achievement of dimensional control and compositional gradients while managing total processing time through optimized cycle duration and number of repetitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of FinFETs with improved performance by confining epitaxy growth, achieving flatter top surfaces, and reducing the likelihood of bridging between FinFETs, thereby enhancing the functional density and efficiency of ICs.
Implementation Method 1
performing an epitaxy to regrow source/drain regions
Data Source
AI summary
A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins. The method further includes recessing the semiconductor fins to form recesses, epitaxially growing a first semiconductor material from the recesses, etching the first semiconductor material, and epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.