FinFET Epitaxy Volume Control via Fin Spacer Height
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to fabricate epitaxy structures with different volumes in device and test regions, where the increased volume in the device region enhances performance, but the merged epitaxy structures in the test region decrease yield.
Innovation Solution
A semiconductor structure and fabrication method where epitaxy structures in the device region are grown to larger volumes by merging adjacent structures, while those in the test region are kept separate with smaller volumes to prevent merging and maintain yield, by controlling fin spacer heights and epitaxy growth processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If fin spacer height is increased to allow larger epitaxy volume, then epitaxy volume increases, but adjacent epitaxy structures may merge in the test region
Solution Approach 1:
The patent implements local quality by setting different fin spacer heights for different regions. The first fin spacers in the device region have a first height that allows epitaxy structures to grow to larger volumes, while the second fin spacers in the test region have a second height that prevents merging. This localized differentiation ensures that each region achieves its desired epitaxy volume while maintaining appropriate separation where needed.
Solution Approach 2:
The patent applies segmentation by dividing the substrate into distinct device and test regions with different fin spacer configurations. This segmentation allows independent optimization of epitaxy growth parameters in each region, enabling the device region to achieve larger epitaxy volumes for performance enhancement while the test region maintains separation for yield preservation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the performance of semiconductor structures by achieving larger epitaxy volumes in the device region while ensuring the test region epitaxy structures remain separated, thus enhancing yield and efficiency.
Implementation Method 1
epitaxial (epi) semiconductor materials to enhance carrier mobility and improve device performance. Forming a FinFET with stressor regions often implements epitaxially grown silicon (Si) to form raised source and drain features
Data Source
AI summary
A semiconductor structure includes a device region and a test region. In the device region, first fin spacers cover sidewalls of a first fin structure and have a first height, and a first epitaxy structure is disposed in the first fin structure, which a portion of the first epitaxy structure is above the first fin spacers and having a first width. In the test region, second fin spacers cover sidewalls of the second fin structure and have a second height, and the second height is greater than the first height. A second epitaxy structure is disposed in the second fin structure, and a portion of the second epitaxy structure is above the second fin spacers and having a second width, which the second width is less than the first width.