FinFET ESD Protection via Parasitic BJT Current Diversion
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Solution Overview
Problem
Metal oxide field effect transistors (MOSFETs) used as electrostatic discharge (ESD) devices face device destruction due to high current density through the channel region during ESD events, particularly under stringent rise time conditions like the charged-device model (CDM), leading to localized overheating and electromigration.
Innovation Solution
The FinFET structure incorporates a well region extending from the drain to the substrate and increases the resistance of the drain region by adjusting the distance between the drain contact and the gate structure, and uses dummy gate structures to divide the drain regions, facilitating ESD current discharge through a parasitic BJT rather than the channel region, thereby dispersing the current and reducing local crowding effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD current flows through the channel region of the MOSFET, then the ESD protection function is activated, but high current density causes localized overheating and electromigration leading to device destruction
Solution Approach 1:
The drain region is divided into multiple drain regions using dummy gate structures, which segments the current path and distributes the current density across multiple locations. This segmentation prevents localized overheating by spreading the thermal load across a wider area, thereby improving device reliability during ESD events.
Solution Approach 2:
The parasitic BJT is utilized as an intermediary mechanism to divert ESD current away from the channel region. By triggering the parasitic BJT during ESD events, the current is redirected through alternative paths (drain regions and substrate) rather than flowing through the vulnerable channel region, thus preventing localized overheating and device destruction.
2Reliability
If the distance between drain contact and gate structure is increased to raise drain region resistance, then ESD current is diverted through parasitic BJT, but device area increases
Solution Approach 1:
The use of dummy gate structures to divide the drain region into multiple segments allows for increased effective resistance without proportionally increasing the overall device area. The segmented structure creates multiple current paths that collectively provide the desired resistance effect while maintaining a compact footprint.
Solution Approach 2:
The resistance of the drain region is modified by changing the geometric parameters (distance between drain contact and gate structure) and doping characteristics. This parameter adjustment optimizes the resistance value to facilitate parasitic BJT triggering while minimizing the area overhead.
3Reliability
If dummy gate structures are used to divide drain regions, then current density is dispersed and localized crowding effects are reduced, but device complexity increases
Solution Approach 1:
Dummy gate structures are introduced to segment the drain region into multiple independent zones. This segmentation disperses the current density across multiple regions, reducing localized crowding effects and improving current distribution uniformity. The segmented structure achieves better thermal and electrical performance while maintaining a relatively simple overall architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the peak current the device can sustain during ESD events, from 5 A to 12 A, by diverting ESD current through the parasitic BJT and dispersing it across a wider area, reducing the risk of device destruction and maintaining functionality under stringent rise time requirements.
Implementation Method 1
During the BSD mode, the voltage across the drain and the source of the ggNMOS reaches the trigger voltage, engages an avalanche breakdown and triggers the parasitic BJT to turn on
Implementation Method 2
The FinFET structure incorporates a well region extending from the drain to the substrate and increases the resistance of the drain region by adjusting the distance between the drain contact and the gate structure
Data Source
AI summary
In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure.