FINFET-Compatible PC-Bounded ESD Diode for 14nm Nodes
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Solution Overview
Problem
Conventional PC-bounded diodes used in planar CMOS technology are not compatible with FINFET process flow, resulting in small junction areas that are inadequate for effectively discharging ESD current density at smaller technology nodes like 14 nm, requiring multiple FINFETs to be connected in parallel, which reduces layout efficiency.
Innovation Solution
The method involves forming a removable gate over an N− doped fin on a substrate, with P+ doped SiGe or Si epitaxially grown on the anode side and N+ doped Si on the cathode side, using hard masks to control growth and increase junction area, allowing for a larger junction area by calculating it as (2×fin height + fin width)×fin length, enhancing area efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PC-bounded diode formation methods are used in FINFET process flow, then the diode structure is formed, but the junction area is too small to effectively discharge ESD current density
Solution Approach 1:
The patent transitions from planar diode formation to three-dimensional FINFET-based diode structure. The diode is formed using the vertical fin structure with source and drain regions doped with opposite polarities, creating a P-N junction that utilizes the vertical dimension of the fin. This dimensional change allows the junction area to be calculated as (2×fin height + fin width)×fin length, significantly increasing the effective area compared to conventional planar approaches.
Solution Approach 2:
The FINFET structure serves dual purposes: as a functional transistor for circuit operation and as the basis for forming the ESD protection diode. The source and drain regions of the FINFET are repurposed to create the P-N junction of the diode, eliminating the need for separate diode structures and maximizing area efficiency while providing both logic functionality and ESD protection.
2Reliability
If multiple FINFETs are connected in parallel to increase junction area, then ESD protection capability is improved, but layout efficiency is reduced
Solution Approach 1:
Each FINFET structure simultaneously provides transistor functionality for circuit operation and serves as a complete ESD protection diode through its doped source and drain regions. This multi-functionality eliminates the need for separate parallel diode structures, achieving high ESD protection capability while maintaining compact layout efficiency.
Solution Approach 2:
The patent merges the transistor and ESD diode functions into a single integrated structure. The FINFET's source and drain regions are doped with opposite polarities to form the P-N junction of the diode, combining what would traditionally require separate components into one unified structure, thereby improving layout efficiency.
3Ease of manufacture
If conventional planar CMOS technology is used, then PC-bounded diodes can be easily formed, but immunity to short-channel effects is insufficient at smaller technology nodes
Solution Approach 1:
The patent adopts the vertical FINFET structure instead of planar CMOS, transitioning from two-dimensional channel control to three-dimensional control. The fin structure provides superior electrostatic control over the channel, improving immunity to short-channel effects while maintaining compatibility with standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of FINFET-compatible ESD diodes with increased junction area, reducing ESD current density and improving layout efficiency, making them suitable for 14 nm technology nodes and beyond.
Implementation Method 1
forming P+ doped SiGe or Si on an anode side of the fin
Implementation Method 2
forming N+ doped Si on a cathode side of the fin
Data Source
AI summary
A semiconductor device is formed having compatibility with FINFET process flow, while having a large enough junction area of to reduce the discharge ESD current density. Embodiments include forming a removable gate over an N− doped fin on a substrate, forming P+ doped SiGe or Si on an anode side of the fin, and forming N+ doped Si on a cathode side of the fin. The area efficiency of the semiconductor device layout is greatly improved, and, thereby, discharge of ESD current density is mitigated.