FinFET ESD Protection via Lateral PN Junction
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Solution Overview
Problem
Conventional electrostatic discharge (ESD) protection devices in FinFET devices face performance degradation due to local hot spots caused by discharge currents flowing through narrow fins, leading to reduced effectiveness in protecting against excessive voltages.
Innovation Solution
A method for manufacturing an ESD protection device involving a semiconductor structure with a pn junction formed in the semiconductor substrate, utilizing a doping process to create a region of opposite conductivity type, which increases the current flow area and prevents local hot spots, including ion implantation and annealing treatments to optimize doping concentrations and electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a pn junction is formed on the fin in a conventional ESD protection device, then the device structure is simple and easy to manufacture, but the discharge current flows through a relatively small cross-sectional area causing local hot spots and performance degradation
Solution Approach 1:
The patent transitions the pn junction formation from a vertical configuration (on the fin) to a lateral configuration (in the semiconductor substrate). This dimensional change allows the junction to extend horizontally across a larger area beneath the fin, increasing the current conduction path from a narrow vertical cross-section to a broader lateral region, thereby dissipating heat more effectively and preventing hot spots.
Solution Approach 2:
The patent divides the ESD protection structure into distinct functional regions: the fin structure for field effect control and the separately formed pn junction in the substrate for current dissipation. This segmentation allows each component to be optimized independently - the fin maintains its narrow profile for device scaling while the substrate junction provides an extended lateral area for safe current flow, resolving the contradiction between compact structure and heat dissipation.
2Area of moving object
If the fin is made relatively narrow to reduce device size, then the CMOS device size is reduced, but the cross-sectional area for discharge current becomes too small causing local hot spots
Solution Approach 1:
The patent resolves the area-temperature contradiction by shifting the current conduction path from the vertical dimension (through the narrow fin) to the lateral dimension (through the substrate). The pn junction is formed extending laterally in the substrate beneath the fin, creating a large horizontal area for current flow while maintaining the fin's narrow vertical profile for compact device size. This dimensional separation allows both small device footprint and effective heat dissipation.
Solution Approach 2:
The patent introduces the semiconductor substrate as an intermediary structure that mediates between the narrow fin and the heat dissipation requirement. The pn junction formed in the substrate acts as a thermal and electrical buffer, providing a large lateral area for current flow and heat distribution without directly increasing the fin's cross-sectional area. This intermediary substrate region absorbs the thermal load while preserving the compact fin structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the risk of performance degradation by ensuring current flows through a larger area, minimizing the occurrence of local hot spots and enhancing the overall performance of the ESD protection device.
Implementation Method 1
performing a doping process on the semiconductor structure to forming a second region in the first region, the second region having a second conductivity type opposite the first conductivity type to form a pn junction in the semiconductor substrate
Implementation Method 2
performing the doping process comprises an ion implantation process; the first conductivity type is P-type, and the second conductivity type is N-type, the ion implantation process includes implanting arsenic ions or phosphorous ions into the semiconductor structure
Implementation Method 3
performing the doping process comprises an ion implantation process... with an energy in a range between 2 keV and 30 keV
Data Source
AI summary
An electrostatic discharge (ESD) protection device includes a semiconductor substrate including a first region of a first conductivity type and a second region of a second conductivity type opposite the first conductivity type, the first region and the second region being adjacent to each other and forming a pn junction in the semiconductor substrate, a semiconductor fin on the semiconductor substrate, and an electrode on the semiconductor fin. The pn junction in the semiconductor substrate has a relatively large area to prevent local hot spots from occurring when a current flows through the ESD protection device, thereby reducing performance degradation of a semiconductor device.