FinFET ESD Device Non-Merging Drain Epitaxy
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Solution Overview
Problem
Conventional ESD devices in integrated circuits, particularly those using FinFET structures, face challenges in providing adequate protection due to the need for a large number of FinFETs to be connected in parallel, making them prone to malfunction if any one FinFET breaks down, and requiring uniform turning on, which is difficult to achieve.
Innovation Solution
The development of a FinFET-based ESD device with a non-merging drain epitaxy region that increases drain resistance, allowing multiple ESD devices to be turned on more uniformly, formed through selective epitaxial growth and specific gate stack configurations, without requiring additional process steps or lithography masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a great number of FinFET devices are connected in parallel to provide high ESD protection capability, then the ESD protection capability is improved, but the reliability deteriorates because the breakdown of any one FinFET may cause the entire ESD protection circuit to malfunction
Solution Approach 1:
The ESD protection circuit is divided into multiple independent ESD devices, each comprising multiple FinFETs connected in parallel. These ESD devices are further connected in series between the first and second power lines, creating segmented protection zones. This segmentation ensures that a breakdown in one ESD device does not affect the entire protection circuit, as other segments remain functional.
Solution Approach 2:
The patent implements a configuration where ESD devices are strategically placed between power lines to provide preemptive protection. The series connection of multiple ESD devices creates redundant protection paths before ESD events can propagate through the circuit, cushioning against potential failures in individual FinFETs.
2Power
If a great number of FinFET devices are connected in parallel to provide high ESD protection capability, then the ESD protection capability is improved, but the device complexity increases
Solution Approach 1:
Multiple FinFET devices are merged into unified ESD device structures that function as integrated protection units. Each ESD device combines multiple FinFETs in parallel, and multiple ESD devices are then connected in series, creating a modular architecture that reduces overall system complexity while maintaining high ESD protection capability.
Solution Approach 2:
The ESD devices serve multiple functions: they provide ESD protection, act as current limiting elements, and function as protective barriers between power lines. This multi-functionality reduces the need for separate dedicated components, thereby reducing overall device complexity.
3Power
If FinFETs are connected in parallel to provide high ESD protection capability, then the ESD protection capability is improved, but the ease of operation worsens because the FinFETs need to be turned on uniformly which is difficult to achieve
Solution Approach 1:
Each ESD device is designed with specific local characteristics including optimized FinFET dimensions, doping profiles, and gate structures. These localized quality adjustments ensure that each ESD device has consistent electrical characteristics, enabling uniform turning on behavior across all devices in the series connection without requiring complex control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables more uniform activation of ESD devices, enhancing their protection capabilities against ElectroStatic Discharge without adding complexity to the manufacturing process, ensuring robustness against potential failures in individual FinFETs.
Implementation Method 1
formed through selective epitaxial growth
Data Source
AI summary
A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material.


