FinFET Fin Patterning With Etch-Adjusting Layers for Uniform Width
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Solution Overview
Problem
The semiconductor industry faces challenges in maintaining uniform fin widths across different pattern densities due to etching variations during the fabrication of fin field effect transistors (finFETs), leading to loading effects that affect device performance.
Innovation Solution
The implementation of an etch-adjusting layer between the substrate and patterned patterning layers, combined with selective precursor use in plasma etching processes, to retard downward etching and enhance lateral etching, resulting in uniform fin structures across regions of varying pattern density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional plasma etching is used without etch-adjusting layers, then the fabrication process is simpler, but fin width uniformity deteriorates across different pattern densities
Solution Approach 1:
An etch-adjusting layer is introduced as an intermediary between the mandrel pattern and the substrate. This layer mediates the etching process by providing a controlled interface that enables uniform fin formation across different pattern densities. The etch-adjusting layer has specific material properties that allow it to modulate etch rates, thereby compensating for loading effects and achieving consistent fin widths regardless of pattern density variations.
Solution Approach 2:
The invention changes the physical and chemical parameters of the etching process by introducing the etch-adjusting layer with specific material composition and thickness. This layer alters the etch rate parameters locally, enabling differential etching control. By adjusting the etch-adjusting layer's properties (material composition, thickness), the process can be tuned to achieve uniform fin widths across isolated and dense regions without changing the fundamental etching chemistry.
2Manufacturing precision
If etch-adjusting layers and selective precursors are used to achieve uniform fin widths, then fin width uniformity improves across pattern densities, but the fabrication process complexity increases
Solution Approach 1:
The etch-adjusting layer is formed in advance before the main fin etching process. This preliminary action prepares the surface with controlled properties that will guide the subsequent etching process. By pre-forming this layer with specific thickness and composition, the actual fin formation etch can proceed with uniform results across different pattern densities, reducing the need for complex real-time process adjustments.
Solution Approach 2:
The etch-adjusting layer provides local quality variation across the wafer surface, with different regions having optimized properties for their specific pattern density requirements. The layer can be selectively formed or have varying thickness in different regions, allowing tailored etching behavior for isolated versus dense regions. This local optimization enables uniform fin formation without requiring global process changes.
3Productivity
If conventional etching is used, then the process is faster and simpler, but loading effects cause non-uniform fin structures in isolated versus dense regions
Solution Approach 1:
The etch-adjusting layer serves as a mediator that decouples the etching speed from the fin formation uniformity. It allows the use of relatively fast etching conditions while the layer itself absorbs the variability in etch rates caused by different pattern densities. The mediator layer converts a potentially problematic high-speed etch process into one that produces uniform fins by compensating for loading effects at the interface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that fin structures are formed with substantially the same width in both dense and isolated regions, mitigating loading effects and enhancing device consistency and performance.
Implementation Method 1
performing a first plasma etching process on the upper patterning layer to form a patterned upper patterning layer
Implementation Method 2
performing a second plasma etching process on the lower patterning layer to form a patterned lower patterning layer
Data Source
AI summary
The present disclosure relates to a method for forming a semiconductor structure includes depositing a dielectric layer on a substrate and depositing a patterning layer on the dielectric layer. The method also includes performing a first etching process on the patterning layer to form a first region including a first plurality of blocks at a first pattern density and a second region including a second plurality of blocks at a second pattern density that is lower than the first pattern density. The method also includes performing a second etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks and etching the dielectric layer and the substrate using the first and second pluralities of blocks to form a plurality of fin structures.